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SSTV16857MTDFAIN/a20100avai14-Bit Register with SSTL-2 Compatible I/O and Reset
SSTV16857MTDXFAIN/a15avai14-Bit Register with SSTL-2 Compatible I/O and Reset


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SSTV16857MTD-SSTV16857MTDX
14-Bit Register with SSTL-2 Compatible I/O and Reset
SSTV16857 • SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset September 2000 Revised April 2004 SSTV16857  SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16857 is a 14-bit register designed for use withCompliant with DDR-I registered module specifications 184 and 232 pin PC1600, 2100, and 2700 DDR DIMMOperates at 2.5V ± 0.2V V DD applications. The SSTVN16857 is a 14-bit register SSTL-2 compatible input and output structure designed for use with 184 and 232 pin PC3200 DDR DIMM Differential SSTL-2 compatible clock inputs applications. These devices have a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatibleLow power mode when device is reset RESET input. These devices have been designed for com- Industry standard 48 pin TSSOP package pliance with the JEDEC DDR module and register specifi- cations. The devices are fabricated on an advanced submicron CMOS process and are designed to operate at power sup- plies of less than 3.6V’s. Ordering Code: Order Number Package Number Package Description SSTV16857MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide SSTVN16857MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Preliminary) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Name Description Q -Q SSTL-2 Compatible Output 1 14 D -D SSTL-2 Compatible Inputs 1 14 RESET Asynchronous LVCMOS Reset Input CK Positive Master Clock Input CK Negative Master Clock Input V Voltage Reference Pin for SSTL Level Inputs REF V Power Supply Voltage for Output Signals DDQ V Power Supply Voltage for Inputs DD Truth Table D Q RESET CK CK n n LX or X or X or L Floating Floating Floating HL ↑↓ L HH ↑↓ H HX L H Q n HX H L Q n L = Logic LOW H = Logic HIGH X = Don’t Care, but not floating unless noted ↑ = LOW-to-HIGH Clock Transition ↓ = HIGH-to-LOW Clock Transition © 2004 DS500387
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