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SSC050-01
I²C Backplane Controller
SSC050-01
Two-Wire Serial Backplane Controller
Data Sheet
Revision 4.0
November 10, 2004
ContentsSSC050-01
Data Sheet
Revision History
Chapter 1 Introduction....................................................................................... 1-1Feature Summary ..............................................................................................................1-2
Typical Applications ...........................................................................................................1-3
FC-AL Drive Enclosure Configuration .......................................................................1-3
General Purpose I/O Configuration ...........................................................................1-3
Chapter 2 Functional Description..................................................................... 2-1Two-wire Serial Interface ...................................................................................................2-1
Control Registers ...............................................................................................................2-2
I/O Logic ............................................................................................................................2-3
Clock Generator ................................................................................................................2-3
Power-On Reset ................................................................................................................2-3
Chapter 3 Pin Description................................................................................. 3-1Functional Signal Grouping ...............................................................................................3-1
Pinout Diagram ..................................................................................................................3-2
Pin Description List ............................................................................................................3-3
Chapter 4 Control Registers............................................................................. 4-1Register Map .....................................................................................................................4-1
Address Map .....................................................................................................................4-4
Control Register Definition ................................................................................................4-6
00h: General Purpose I/O Port 0 Data (GPD0) .........................................................4-6
01h: General Purpose I/O Port 1 Data (GPD1) .........................................................4-7
02h: General Purpose I/O Port 2 Data (GPD2) .........................................................4-7
03h: General Purpose I/O Port 3 Data (GPD3) .........................................................4-8
04h: General Purpose I/O Port 4 Data (GPD4) .........................................................4-8
10h: I/O Port 0 Data Direction (DDP0) ......................................................................4-9
11h: I/O Port 1 Data Direction (DDP1) ......................................................................4-9
12h: I/O Port 2 Data Direction (DDP2) ....................................................................4-10
13h: I/O Port 3 Data Direction (DDP3) ....................................................................4-10
14h: I/O Port 4 Data Direction (DDP4) ....................................................................4-11
20h: Port Bypass Control 0 (PBC0) .......................................................................4-12
21h: Port Bypass Control 1 (PBC1) .......................................................................4-13
22h: Port Bypass Control 2 (PBC2) .......................................................................4-14
23h: Port Bypass Control 3 (PBC3) .......................................................................4-15
24h: Port Bypass Control 4 (PBC4) .......................................................................4-16
25h: Port Bypass Control 5 (PBC5) .......................................................................4-17
Contents
ContentsSSC050-01
Data Sheet 26h: Port Bypass Control 6 (PBC6) .......................................................................4-18
27h: Port Bypass Control 7 (PBC7) .......................................................................4-19
30h: Fan Speed Control 0 Register (FSC0) ............................................................4-20
31h: Fan Speed Count Overflow 0 (FSCO0, R/W) .................................................4-22
32h: Fan Speed Current Count 0 (FSCC0) ............................................................4-23
34h: Fan Speed Control 1 (FSC1) ..........................................................................4-24
35h: Fan Speed Count Overflow 1 (FSCO1) ..........................................................4-26
36h: Fan Speed Current Count 1 (FSCC1) ............................................................4-27
38h: Fan Speed Control 2 (FSC2) ..........................................................................4-28
39h: Fan Speed Count Overflow 2 (FSCO2) ..........................................................4-30
3Ah: Fan Speed Current Count 2 (FSCC2) ...........................................................4-31
3Ch: Fan Speed Control 3 (FSC3) .........................................................................4-32
3Dh: Fan Speed Count Overflow 3 (FSCO3) .........................................................4-34
3Eh: Fan Speed Current Count 3 (FSCC3) ...........................................................4-35
80h-87h: Bit Control Port 0 Registers (BCP00-BCP07) .........................................4-36
90h-97h: Bit Control Port 1 Registers (BCP10-BCP17) .........................................4-38
98h-9Bh: Pulse Width Modulation Control Registers (PWMC0-PWMC3) .............4-40
A0h-A7h: Bit Control Port 2 Registers (BCP20-BCP27) ........................................4-42
B0h-B7h: Bit Control Port 3 Registers (BCP30-BCP37) ........................................4-44
C0h-C7h: Bit Control Port 4 Registers (BCP40-BCP47) ........................................4-46
F8h: Backplane Controller Interrupt Status (BCIS) ................................................4-48
FCh: Backplane Controller Test (BCT) ...................................................................4-49
FDh: Backplane Controller Option (BCO) ..............................................................4-50
FFh: Backplane Controller Version (VER) ..............................................................4-51
Chapter 5 Electrical Characteristics................................................................. 5-1Maximum Ratings ..............................................................................................................5-1
DC Characteristics ............................................................................................................5-1
AC Characteristics .............................................................................................................5-5
External Clock Timing ...............................................................................................5-5
Two-wire Serial Interface Operation ..........................................................................5-7
Oscillator Requirements ............................................................................................5-7
External Reset Circuit ...............................................................................................5-9
Optional External Tach Filter ...................................................................................5-10
Chapter 6 Mechanical Drawing......................................................................... 6-1
Chapter 7 Ordering Information........................................................................ 7-1
SSC050-01
Data Sheet
REVISION HISTORY
RevisionDateSectionChange1.0111/4/03AllInitial Revision
1.011/10/04Updated
4.011/10/04Data Manual migrated to Data Sheet status
IntroductionSSC050-01
Data Sheet
Chapter 1IntroductionThe SSC050-01 is a I/O-intensive peripheral device which is intended to be a portion of a cost effective
FC-AL, SCSI, SAS or SATA enclosure management solution. The device contains an address
programmable two wire serial interface, a block of control and status registers, I/O port control logic,
specialized port bypass control logic and a clock generation block. Along with an external crystal, the
device can be configured to support up to 40 bits of general purpose I/O or 16 bits of general purpose I/
O, 16 bits of port bypass control (8 pairs supporting 8 drives), 4 fan speed monitoring inputs and 4 pulse
width modulated outputs.
The SSC050-01 is capable of supporting various combinations of individual PBC/CRU/SDU functions
as well as integrated solutions. The control register portion of the device allows the user to individually
program each I/O pin as an input, output or open source/drain output. Additional control features
include selectable flash rates for direct LED drive, input edge detection for interrupt generation, fan
speed monitoring and pulse width modulated outputs. The addressing capability of the SSC050-01
includes three pins, which are used for device addressing, as well as one pin, which can be used to select
two device type identifiers. Sixteen devices can be used in a single two-wire serial interface system.
IntroductionSSC050-01
Feature SummaryData Sheet
FEATURE SUMMARYUp to 40 bits of user-definable, bidirectional general purpose I/O Integrated Port Bypass, Clock Recovery and Signal Detect support for up to 8 drivesFour programmable fan speed monitoring inputs5 volt tolerant Interrupt output eliminates polling requirementsSelectable direct LED drive flashing capabilityPin-programmable addressing for up to 16 devices on a single serial bus5 volt tolerant slave mode two wire serial interface20% of package pins are power and groundFour programmable pulse width modulation outputsEnhanced fan speed monitor input filters
Figure 1-1.Chip Block Diagram
Interrupt Priority and Control
I/O Ports
P1.0 - P1.7
Power
On Reset
OSCI
OSCO
SDA
SCL
A2-A0
ASEL
INT#
P2.0 - P2.7P0.0 - P0.7P3.0 - P3.7P4.0 - P4.7
Port Bypass
Control
Fan Speed
Sensors
and PWM
Control
I/O Control
and LED
Flashing
Two-Wire
Serial Slave
Interface
Clock
Generator
and Dividers
IntroductionSSC050-01
Typical ApplicationsData Sheet
TYPICAL APPLICATIONS
FC-AL Drive Enclosure ConfigurationBasic port bypass configurationSupport for up to 128 drivesBackplane controller supports up to two sets of CRU/SDU functions and 8 drivesSixteen Backplane controllers can be simultaneously attached to the serial busFour drive implementation shown - four channel PBC with two CRU/SDU functionsGeneral purpose I/O lines used for drive control/status and system control/status
General Purpose I/O ConfigurationControlled by general purpose Microcontroller with two wire serial interfaceSupport for up to 640 I/O linesBackplane controller supports up to 40 I/O linesSixteen backplane controllers can be simultaneously attached to the serial bus
Four backplane controller implementation shown with shared open drain interrupt
Figure 1-2.Single Loop, Single Controller with Four Drives
Drive Bay 1
Drive Bay 2
Drive Bay 3
Drive Bay 4
VSC7147
MAXIM
Backplane
Controller
(SSC050-01)
Local I/O (x26)
MAXIM
Embedded
Controller
(VSC120)
Temperature
Sensor (LM75)
Flash
(512K x 16)Two-Wire Serial
InterfacePBC_EN1
PBC_EN2
PBC_EN3
PBC_EN4
Power Supplies
LEDs (x16)
PBC_EN
Fans (x4)
Cu or
Optics
X24C16
EEPROM
Tach in
PWM out
IntroductionSSC050-01
Typical ApplicationsData Sheet
Figure 1-3.Four Backplane Controllers, 160 Bidirectional I/O Lines
MAXIM
Backplane
Controller
(SSC050-01)
MicroController
with
Two Wire
Serial I/F
Two Wire Serial I/F
MAXIM
Backplane
Controller
(SSC050-01)
Interrupt(optional)
MAXIM
Backplane
Controller
(SCC050-01)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
MAXIM
Backplane
Controller
(SCC050-01)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
I/O (x8)
Functional DescriptionSSC050-01
Two-wire Serial InterfaceData Sheet
Chapter 2FUNCTIONAL DESCRIPTIONThe SSC050-01 is composed of five major functional blocks; a slave mode two-wire serial interface, a
block of control registers, general purpose I/O and specialized port bypass control logic, a clock
generator and power-on reset control logic. The SSC050-01 fully supports a generic two-wire serial
interface and is compatible with other industry standard devices which also support this interface at both
100K and 400K bits per second.
TWO-WIRE SERIAL INTERFACEThe device supports a single slave mode two-wire serial interface. All inter-chip communication to a
microcontroller takes place over this bus. The interface supports a three-bit address bus, which allows
the user to select one of eight possible addresses. The address bus is compared to bits three through one
of the slave address byte, which is the first byte transmitted to the device after a start condition. The
SSC050-01 supports two pin selectable four-bit device type identifier values, 1000b and 1100b. The
address bits and the device identifier allow the use of up to 16 devices on a single two-wire serial
interface. The serial interface control logic includes the slave state machine, address comparison logic,
serial to parallel and parallel to serial conversion, register read/write control and filtering for the clock
and data line.
A read or write transaction is determined by the least significant bit (R/W) of the first byte transferred.
Write accesses require a three-byte transfer. The first byte is the slave address with the R/W bit low, the
second byte contains the register address and the third byte is the write data. Read accesses require a
four-byte transfer since data transfer direction can not change after receipt of the slave address byte. The
first byte is the slave address with the R/W bit low, the second byte contains the register address, the
third byte is a repeated slave address with the R/W bit high and the fourth byte is the read data. If the
transaction is a write, the data will be latched into the appropriate register during the acknowledge of the
third byte. All transactions to or from the device complete during the acknowledge of the third byte
allowing the user to immediately initiate another transfer to the device. Sequential read or write
transactions are allowed and are extensions of the above protocol with additional data bytes added to the
end of the transaction. All sequential transactions will cause the internal address to increment by one
regardless of the register address.
Functional DescriptionSSC050-01
Control RegistersData Sheet
CONTROL REGISTERSThe SSC050-01 contains five groups of control registers. Each group supports a specific function within
the device as follows; the first group is the port data registers, the second is the data direction registers,
the third contains special bit control features, the fourth supports the port bypass control function and
the fifth supports fan speed monitoring. Currently the device contains 78 registers to support all required
functions. In normal I/O operation, each eight-bit group of I/O pins are controlled by a pair of registers,
Port Data and Data Direction. The use of these pairs of registers allows each I/O line to be individually
configured as an input with internal pull-up, output or open drain output with internal pull-up.
The bit control features are enabled through a separate register for each I/O pin. The Bit Control
registers allow the user to independently configure each I/O pin to enable one of the special control
features as well as control Port Data and Data Direction (which are shadowed copies of the standard
control bits found in the Port Data and Data Direction registers). Each I/O pin which has been
configured as an input can also be configured to assert the open drain interrupt pin when a rising edge, a
falling edge or either edge is detected on the I/O pin. An Interrupt Status register provides the user with
a binary indication of which I/O pin is the source of the current interrupt. Each I/O pin which is
configured as an output can automatically generate one of seven selectable flashing rates, which are
normally driven in an open drain mode. By providing all I/O control capability in a single register, the
user can control the operation of the I/O on a pin-by-pin basis.
The Port Bypass registers control the operation of a selected group of I/O lines which can be dedicated
to support various combinations of individual PBC/CRU/SDU functions as well as integrated solutions.
Enabling port bypass control causes the normal or bit control register settings to be overridden and any
further changes to the affected registers will have no effect. Each Port Bypass Control register will
automatically configure the I/O lines to support a Force Bypass output and a Signal Detected input.
The Fan Speed registers control the operation of four programmable inputs which can be used to
monitor signals from fans equipped with tachometer outputs. Enabling fan speed control causes the
normal or bit control register settings to be overridden and any further changes to the affected registers
will have no effect. Each group of three registers provides the capability to enable the function, establish
a user defined RPM overflow value which indicates a failure and determine the current RPM value of
the fan. The digital filters on the fan speed inputs can optionally be enabled to increase the normal 100
to 200 nanosecond filter to 400 to 500 nanoseconds.
The Pulse Width Modulation Control registers enable internal logic to provide duty cycles of 0% to
100% in 3% increments at default frequencies of 26KHz, 52KHz and 104KHz. Optionally, the PWM
outputs can be programmed for three additional frequency ranges of 5.2KHz, 10.4KHz and 20.8KHz or
1.04KHz, 2.08KHz and 4.16KHz or 208Hz, 416Hz and 833Hz. These outputs can vary the speed of up
to four fans through the use of external drivers and power MOSFETs or pulse width to voltage
converters. They can also be used to support other pulse width modulated requirements within the
system.
Functional DescriptionSSC050-01
I/O LogicData Sheet
I/O LOGICEach general purpose I/O pin is controlled by a set of registers in the Control Register Block. The I/O
supports a high current drive output buffer, which can be configured as a totem pole or open drain driver.
The input section of the I/O supports TTL signaling and includes an internal weak pull-up device. This
allows unused I/O pins to be left unconnected without high current drain issues. The port bypass control
I/O pins which are shared with Port 3 and Port 4 are generated using the same buffer logic as the other
ports. When enabled in port bypass control mode, internal logic overrides the existing configuration,
with each I/O pin dedicated to the specific port bypass function. All I/O lines default as inputs with the
weak internal pull-up enabled.
CLOCK GENERATORClock generation for the device is composed of an internal oscillator, divider circuits and a distribution
network. The primary clock frequency of 10.0MHz is used for filtering incoming serial interface signals
and interrupt sources as well as clocking the slave state machine. Divided clocks provide the source for
LED flash rate generators. Logic within the SSC050-01 synchronizes the divided clocks between
devices attached to the same two-wire serial bus with no more than 200 nanoseconds of skew. Multiple
devices can then be used to drive different LED's at the same frequency, providing a synchronized
visible indication. The oscillator provides a stable clock source for the device and requires the use of an
off chip crystal and related passive components or external clock source. There are no programmable
options related to clock generation except the selection of the seven fixed LED Flashing rates. The
SSC050-01 can operate at frequencies other than 10.0MHz and continue to meet both the standard mode
(100KHz) and fast mode (400KHz) serial interface timings. Frequencies from 8.0MHz to 12.5MHz are
allowable as long as they meet the AC timing requirements listed in section 5.3.1 of this manual.
Operation of the LED flashing circuits, fan speed counters and pulse width modulated outputs will be
affected by a change in base operating frequency. The user must scale the expected operating parameters
by the change in frequency from a nominal 10.0MHz. As and example, operating the SSC050-01 at
8.0MHz will cause the LED flashing circuits, fan speed counters and pulse width modulated outputs to
operate 25% slower than normal.
POWER-ON RESETPower-On Reset is accomplished by the use of logic internal to the device. No external components are
required. After power-on, the serial interface state machine will always return an idle state waiting for a
start condition to appear on the SCL and SDA pins. A proper power-on reset sequence will clear the
serial interface state machine, the clock generators, the control registers, the I/O control logic and the
port bypass control logic. The divided clocks used for LED flash rate generation will also be in a known
state. An external reset circuit utilizing the TEST1 and ASEL pins can be developed as an option to the
internal Power-On Reset logic. Regardless of the effectiveness of either power-on reset sequence, it is
highly recommended that the control registers and I/O control logic be cleared through the Soft Reset
Register bit. This can be accomplished by writing a 80h to the BCT Register (FCh) followed
immediately by a STOP condition. This bit is self resetting and will not require further attention.
Pin DescriptionSSC050-01
Functional Signal GroupingData Sheet
Chapter 3Pin DescriptionThe SSC050-01 is packaged in a 64-pin PQFP. All pins have been placed to optimize their connection to
external components. Power and ground distribution has also been optimized for core and high current I/
O connections. All serial interface pins as well as the interrupt output are 5 volt tolerant. VDD and
VDD2 should be connected to a 3.3 volt supply with no more than 10% tolerances.
FUNCTIONAL SIGNAL GROUPING
Figure 3-1.Functional Signal Grouping
P1.7-P1.0
P0.7-P0.0
P3.7-P3.0
P2.7-P2.0
INT#
A2-A0
SCL
ASEL
SDA
TEST0
TEST1
TEST2
I/O
Ports
Clock
Serial
Interface
P4.7-P4.0
Functional
TestInterrupt
OSCI
OSCO
Pin DescriptionSSC050-01
Pinout DiagramData Sheet
PINOUT DIAGRAM
Figure 3-2.Pinout Diagram
VDD
1VDD
SSC050-01
P0.0
TEST2
TEST1
TEST0
VSS
VSS2
OSCO
P4.6
VDD
VSS
SDA
P4.7
INT#
OSCI
SCL
ASEL
P4.
P4.
P4.
P4.
P4.
P4.
P3.
P3.
P3.
P3.
P3.
SS2
P0.2P0.1P0.3P0.5P0.4P0.6P0.7P1.0P1.2P1.1P1.3VDD2
P1.4
VSS
P1.5
P1.7
P1.6
P2.0
P2.2
P2.1
P2.3
P2.5
P2.4
P2.6
P3.0
P2.7
P3.1
VDD
P3.2
VSS
Pin DescriptionSSC050-01
Pin Description ListData Sheet
PIN DESCRIPTION LISTThe following pin descriptions are grouped by function.
Table 3-1:Serial Interface
Pin NamesPin No.TypePin DescriptionA2-A09-7InputsAddress Select Bus
This pin group provides the value, which will be compared to bits
3 through 1 of the serial slave address. These pins should be
strapped to VDD or VSS to provide the appropriate binary value.
ASEL12InputDevice Type Address Select
This pin provides the ability to select between two-device type
address values in the serial slave address. When tied to VSS,
the device type address is 1000b and when tied to VDD, the
device type address is 1100b.
SCL13InputTwo-wire Serial Interface Clock
This pin is used by the device to latch the data present on the
SDA pin. This pin in conjunction with the SDA pin also deter-
mines Start and Stop conditions on the serial bus.
SDA14BidirectionalTwo-wire Serial Interface Data
This pin is used to transfer all serial data into and out of the
device. This pin in conjunction with the SCL pin also determines
Start and Stop conditions on the serial bus.
Table 3-2:Clock
Pin NamesPin No.TypePin DescriptionOSCI11InputOscillator Input
This pin is connected to one side of an external 10.0MHz crystal
to produce the clock required for serial signal filtering, state
machine clocking and flash rate generation. An alternate exter-
nal 3.3 volt 10.0MHz clock source can be connected to this pin.
OSCO10OutputOscillator Output
This pin is connected to the other side of an external 10.0MHz
crystal. When an alternate external clock source is used, this pin
should be left unconnected.
Table 3-3:Interrupt
Pin NamesPin No.TypePin DescriptionINT#15Open-Drain
Output
Interrupt
This open-drain output can be used to signal the microcontroller
that an event has occurred on an I/O pin which is configured as
an input or that a special function event has occurred. This pin
can be wire ORed with other open drain outputs to provide a sin-
gle interrupt input source.
Pin DescriptionSSC050-01
Pin Description ListData Sheet
Table 3-4:I/O Ports
Pin NamesPin No.TypePin DescriptionP0.7-P0.057-64BidirectionalI/O Port 0
Port 0 is a dedicated eight-bit bidirectional I/O port. The user
can select between an input, totem pole output or open-drain
output. Additional capability to detect input edge changes and
select various output flashing rates is also available.
P1.7-P1.046-49,
BidirectionalI/O Port 1
Port 1 is a dedicated eight-bit bidirectional I/O port. The user
can select between an input, totem pole output or open-drain
output. Additional capability to detect input edge changes and
select various output flashing rates is also available.
P2.7-P2.0
(Tach Inputs
and PWM out-
puts)
38-45BidirectionalI/O Port 2
Port 2 is an eight-bit bidirectional I/O port. The user can select
between an input, totem pole output or open-drain output. Addi-
tional capability to detect input edge changes and select various
output flashing rates is also available. Through control register
setup, P2.7-P2.4 can be dedicated to monitoring fans equipped
with tachometer outputs. Through control register setup, P2.3-
P2.0 can be dedicated to controlling fan speed utilizing pulse
width modulated outputs.
P3.7-P3.0
(Bypass I/O)
27-31,
BidirectionalI/O Port 3
Port 3 is a shared eight bit bidirectional I/O port which can be
used as a general purpose I/O port or as Port Bypass control.
The user can select between an input, totem pole output or
open-drain output. Additional capability to detect input edge
changes and select various output flashing rates is also availa-
ble. Through control register setup, four two-bit portions of this
port can be dedicated to the control of a combination of PBC/
CRU/SDU functions. Any combination of port bypass control
functions can be enabled with the remaining I/O pins used for
general purpose functions.
P4.7-P4.0
(Bypass I/O)
16, 17,
BidirectionalI/O Port 4
Port 4 is a shared eight bit bidirectional I/O port which can be
used as a general purpose I/O port or as Port Bypass control.
The user can select between an input, totem pole output or
open-drain output. Additional capability to detect input edge
changes and select various output flashing rates is also availa-
ble. Through control register setup, four two-bit portions of this
port can be dedicated to the control of a combination of PBC/
CRU/SDU functions. Any combination of port bypass control
functions can be enabled with the remaining I/O pins used for
general purpose functions.
Table 3-5:Test
Pin NamesPin No.TypePin DescriptionTEST2-
TEST0
6-4InputFunctional Test
These inputs allow the device to be placed in specific test
modes for device level testing. These inputs should be con-
nected to VSS for normal operation.
Pin DescriptionSSC050-01
Pin Description ListData Sheet
Table 3-6:Supply
Pin NamesPin No.TypePin DescriptionVDD1, 19, 34,
PowerI/O Power
These pins are the power sources for the I/O drivers of all non-
analog output and bidirectional pins.
VSS3, 18, 33,
GroundI/O Ground
These pins are the ground connections for the I/O drivers of all
non-analog output and bidirectional pins.
VDD220, 52PowerDigital Core Power
These pins are the power sources for the digital core logic and
receivers of all non-analog input and bidirectional pins.
VSS22, 32GroundDigital Core Ground
These pins are the ground connections for the digital core logic
and receivers of all non-analog input and bidirectional pins.
Control RegistersSSC050-01
Register MapData Sheet
Chapter 4CONTROL REGISTERSThis section contains descriptions for the device-specific control registers. All register locations are
fixed within the device and are mapped for easy access as well as future enhancements.
The control register section is separated into three sub-sections; a register map, an address map and the
bit level description of all registers. The register map lists all registers by operating address. The address
map shows the relative layout of all control registers. All registers can be accessed at any time and no
register function will interfere with the operation of the serial interface. However, changing register bits
will have an immediate effect on the respective I/O lines.
REGISTER MAP
Table 4-1:Register Map
Data Memory
Address
Read/WriteLabelDescription00hR/WGPD0General Purpose I/O Port 0 Data Register
01hR/WGPD1General Purpose I/O Port 1 Data Register
02hR/WGPD2General Purpose I/O Port 2 Data Register
03hR/WGPD3General Purpose I/O Port 3 Data Register
04hR/WGPD4General Purpose I/O Port 4 Data Register
10hR/WDDP0I/O Port 0 Data Direction Register
11hR/WDDP1I/O Port 1 Data Direction Register
12hR/WDDP2I/O Port 2 Data Direction Register
13hR/WDDP3I/O Port 3 Data Direction Register
14hR/WDDP4I/O Port 4 Data Direction Register
20hR/WPBC0Port Bypass Control 0 Register
21hR/WPBC1Port Bypass Control 1 Register
22hR/WPBC2Port Bypass Control 2 Register
23hR/WPBC3Port Bypass Control 3 Register
Control RegistersSSC050-01
Register MapData Sheet 24hR/WPBC4Port Bypass Control 4 Register
25hR/WPBC5Port Bypass Control 5 Register
26hR/WPBC6Port Bypass Control 6 Register
27hR/WPBC7Port Bypass Control 7 Register
30hR/WFSC0Fan Speed Control 0 Register
31hR/WFSCO0Fan Speed Count Overflow 0 Register
32hRFSCC0Fan Speed Current Count 0 Register
34hR/WFSC1Fan Speed Control 1 Register
35hR/WFSCO1Fan Speed Count Overflow 1 Register
36hRFSCC1Fan Speed Current Count 1 Register
38hR/WFSC2Fan Speed Control 2 Register
39hR/WFSCO2Fan Speed Count Overflow 2 Register
3AhRFSCC2Fan Speed Current Count 2 Register
3ChR/WFSC3Fan Speed Control 3 Register
3DhR/WFSCO3Fan Speed Count Overflow 3 Register
3EhRFSCC3Fan Speed Current Count 3 Register
80hR/WBCP00Bit Control Port 0 - Bit 0 Register
81hR/WBCP01Bit Control Port 0 - Bit 1 Register
82hR/WBCP02Bit Control Port 0 - Bit 2 Register
83hR/WBCP03Bit Control Port 0 - Bit 3 Register
84hR/WBCP04Bit Control Port 0 - Bit 4 Register
85hR/WBCP05Bit Control Port 0 - Bit 5 Register
86hR/WBCP06Bit Control Port 0 - Bit 6 Register
87hR/WBCP07Bit Control Port 0 - Bit 7 Register
90hR/WBCP10Bit Control Port 1 - Bit 0 Register
91hR/WBCP11Bit Control Port 1 - Bit 1 Register
92hR/WBCP12Bit Control Port 1 - Bit 2 Register
93hR/WBCP13Bit Control Port 1 - Bit 3 Register
94hR/WBCP14Bit Control Port 1 - Bit 4 Register
95hR/WBCP15Bit Control Port 1 - Bit 5 Register
96hR/WBCP16Bit Control Port 1 - Bit 6 Register
97hR/WBCP17Bit Control Port 1 - Bit 7 Register
Table 4-1:Register Map (continued)
Data Memory
Address
Read/WriteLabelDescription
Control RegistersSSC050-01
Register MapData Sheet 98hR/WPWMC0Pulse Width Modulation Control 0 Register
99hR/WPWMC1Pulse Width Modulation Control 1 Register
9AhR/WPWMC2Pulse Width Modulation Control 2 Register
9BhR/WPWMC3Pulse Width Modulation Control 3 Register
A0hR/WBCP20Bit Control Port 2 - Bit 0 Register
A1hR/WBCP21Bit Control Port 2 - Bit 1 Register
A2hR/WBCP22Bit Control Port 2 - Bit 2 Register
A3hR/WBCP23Bit Control Port 2 - Bit 3 Register
A4hR/WBCP24Bit Control Port 2 - Bit 4 Register
A5hR/WBCP25Bit Control Port 2 - Bit 5 Register
A6hR/WBCP26Bit Control Port 2 - Bit 6 Register
A7hR/WBCP27Bit Control Port 2 - Bit 7 Register
B0hR/WBCP30Bit Control Port 3 - Bit 0 Register
B1hR/WBCP31Bit Control Port 3 - Bit 1 Register
B2hR/WBCP32Bit Control Port 3 - Bit 2 Register
B3hR/WBCP33Bit Control Port 3 - Bit 3 Register
B4hR/WBCP34Bit Control Port 3 - Bit 4 Register
B5hR/WBCP35Bit Control Port 3 - Bit 5 Register
B6hR/WBCP36Bit Control Port 3 - Bit 6 Register
B7hR/WBCP37Bit Control Port 3 - Bit 7 Register
C0hR/WBCP40Bit Control Port 4 - Bit 0 Register
C1hR/WBCP41Bit Control Port 4 - Bit 1 Register
C2hR/WBCP42Bit Control Port 4 - Bit 2 Register
C3hR/WBCP43Bit Control Port 4 - Bit 3 Register
C4hR/WBCP44Bit Control Port 4 - Bit 4 Register
C5hR/WBCP45Bit Control Port 4 - Bit 5 Register
C6hR/WBCP46Bit Control Port 4 - Bit 6 Register
C7hR/WBCP47Bit Control Port 4 - Bit 7 Register
F8hR/WBCISBackplane Controller Interrupt Status Register
FChR/WBCTBackplane Controller Test Register
FDhR/WBCOBackplane Controller Option Register
FFhRVERBackplane Controller Version Register
Table 4-1:Register Map (continued)
Data Memory
Address
Read/WriteLabelDescription
Control RegistersSSC050-01
Address MapData Sheet
ADDRESS MAP
Table 4-2:Address Map
11b10b01b00bAddressGPD3GPD2GPD1GPD000h
reservedreservedreservedGPD404h
reservedreservedreservedreserved08h
reservedreservedreservedreserved0Ch
DDP3DDP2DDP1DDP010h
reservedreservedreservedDDP414h
reservedreservedreservedreserved18h
reservedreservedreservedreserved1Ch
PBC3PBC2PBC1PBC020h
PBC7PBC6PBC5PBC424h
reservedreservedreservedreserved28h
reservedreservedreservedreserved2Ch
reservedFSCC0FSCO0FSC030h
reservedFSCC1FSCO1FSC134h
reservedFSCC2FSCO2FSC238h
reservedFSCC3FSCO3FSC33Ch
reservedreservedreservedreserved40h-7Ch
BCP03BCP02BCP01BCP0080h
BCP07BCP06BCP05BCP0484h
reservedreservedreservedreserved88h
reservedreservedreservedreserved8Ch
BCP13BCP12BCP11BCP1090h
BCP17BCP16BCP15BCP1494h
PWMC3PWMC2PWMC1PWMC098h
reservedreservedreservedreserved9Ch
BCP23BCP22BCP21BCP20A0h
BCP27BCP26BCP25BCP24A4h
reservedreservedreservedreservedA8h
reservedreservedreservedreservedACh
BCP33BCP32BCP31BCP30B0h
Control RegistersSSC050-01
Address MapData Sheet BCP37BCP36BCP35BCP34B4h
reservedreservedreservedreservedB8h
reservedreservedreservedreservedBCh
BCP43BCP42BCP41BCP40C0h
BCP47BCP46BCP45BCP44C4h
reservedreservedreservedreservedC8h-F4h
reservedreservedreservedBCISF8h
VERreservedBCOBCTFCh
Table 4-2:Address Map (continued)
11b10b01b00bAddress
Control RegistersSSC050-01
Control Register DefinitionData Sheet
CONTROL REGISTER DEFINITIONThe register definition provides a bit-level description of all register bits including power-on and default
values. The terms "set" and "assert" refer to bits which are programmed to a binary one. The terms
"reset", "de-assert" and "clear" refer to bits which are programmed to a binary zero. Reserved bits are
represented by "RES" and will always return an unknown value and should be masked. Any bits which
are reserved should never be set to a binary one. These bits may be defined in future versions of the
device.
00h: General Purpose I/O Port 0 Data (GPD0)
Register Name:GPD0
Address:00h
Reset Value:XXXX_XXXXb
DescriptionGeneral Purpose I/O Port 0 Data
76543210General Purpose Data
Bit(s)Bit LabelAccessDescription7:0GPD0.7-0R/WWhen the I/O pin has been enabled as an output, writing these bits determines the
data value which will be present on the corresponding I/O pin. If the I/O pin has been
enabled as an input, reading these register bits will represent the current voltage
applied to the pin. At no time will the bits directly represent the value latched into the
data register. If a pin is enabled as an input and there is no signal applied, weak
internal pull-up resistors will hold the pin at a binary one. After a reset or power-on,
the register bits will be set to a binary one, but the value returned from a register
read will be the level applied to the pin since by default each pin is an input.
Figure 4-1.I/O Port Block Diagram
FILTER
QI/O Port
GPD Read Data
DD Write Data
DD Read Data
GPD Write Data
I/O Port Block Diagram
Control RegistersSSC050-01
Control Register DefinitionData Sheet
01h: General Purpose I/O Port 1 Data (GPD1)
02h: General Purpose I/O Port 2 Data (GPD2)
Register Name:GPD1
Address:01h
Reset Value:XXXX_XXXXb
DescriptionGeneral Purpose I/O Port 1 Data
76543210General Purpose Data
Bit(s)Bit LabelAccessDescription7:0GPD0.7-0R/WWhen the I/O pin has been enabled as an output, writing these bits determines the
data value which will be present on the corresponding I/O pin. If the I/O pin has been
enabled as an input, reading these register bits will represent the current voltage
applied to the pin. At no time will the bits directly represent the value latched into the
data register. If a pin is enabled as an input and there is no signal applied, weak
internal pull-up resistors will hold the pin at a binary one. After a reset or power-on,
the register bits will be set to a binary one, but the value returned from a register
read will be the level applied to the pin since by default each pin is an input.
Register Name:GPD2
Address:02h
Reset Value:XXXX_XXXXb
DescriptionGeneral Purpose I/O Port 2 Data
76543210General Purpose Data
Bit(s)Bit LabelAccessDescription7:0GPD0.7-0R/WWhen the I/O pin has been enabled as an output, writing these bits determines the
data value which will be present on the corresponding I/O pin. If the I/O pin has been
enabled as an input, reading these register bits will represent the current voltage
applied to the pin. At no time will the bits directly represent the value latched into the
data register. If a pin is enabled as an input and there is no signal applied, weak
internal pull-up resistors will hold the pin at a binary one. After a reset or power-on,
the register bits will be set to a binary one, but the value returned from a register
read will be the level applied to the pin since by default each pin is an input.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
03h: General Purpose I/O Port 3 Data (GPD3)
04h: General Purpose I/O Port 4 Data (GPD4)
Register Name:GPD3
Address:03h
Reset Value:XXXX_XXXXb
DescriptionGeneral Purpose I/O Port 3 Data
76543210General Purpose Data
Bit(s)Bit LabelAccessDescription7:0GPD0.7-0R/WWhen the I/O pin has been enabled as an output, writing these bits determines the
data value which will be present on the corresponding I/O pin. If the I/O pin has been
enabled as an input, reading these register bits will represent the current voltage
applied to the pin. At no time will the bits directly represent the value latched into the
data register. If a pin is enabled as an input and there is no signal applied, weak
internal pull-up resistors will hold the pin at a binary one. After a reset or power-on,
the register bits will be set to a binary one, but the value returned from a register
read will be the level applied to the pin since by default each pin is an input.
Register Name:GPD4
Address:04h
Reset Value:XXXX_XXXXb
DescriptionGeneral Purpose I/O Port 4 Data
76543210General Purpose Data
Bit(s)Bit LabelAccessDescription7:0GPD0.7-0R/WWhen the I/O pin has been enabled as an output, writing these bits determines the
data value which will be present on the corresponding I/O pin. If the I/O pin has been
enabled as an input, reading these register bits will represent the current voltage
applied to the pin. At no time will the bits directly represent the value latched into the
data register. If a pin is enabled as an input and there is no signal applied, weak
internal pull-up resistors will hold the pin at a binary one. After a reset or power-on,
the register bits will be set to a binary one, but the value returned from a register
read will be the level applied to the pin since by default each pin is an input.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
10h: I/O Port 0 Data Direction (DDP0)
11h: I/O Port 1 Data Direction (DDP1)
Register Name:DDP0
Address:10h
Reset Value:1111_1111b
DescriptionI/O Port 0 Data Direction
76543210Data Direction
Bit(s)Bit LabelAccessDescription7:0DDP0.7-0R/WData Direction
These bits determine the direction of the data flow through the I/O pin.
To enable the respective I/O pin as an input, set the appropriate bit. To enable the
respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individ-
ually configured as a true bidirectional function. Additionally, an open-drain or open-
source function can be developed by resetting or setting the appropriate data bit and
using the data direction bit as the programmed data value.
After a reset or power-on, these bits will be set to a binary one, enabling the I/O as
an input with weak pull-up.
Register Name:DDP1
Address:11h
Reset Value:1111_1111b
DescriptionI/O Port 1 Data Direction
76543210Data Direction
Bit(s)Bit LabelAccessDescription7:0DDP0.7-0R/WData Direction
These bits determine the direction of the data flow through the I/O pin.
To enable the respective I/O pin as an input, set the appropriate bit. To enable the
respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individ-
ually configured as a true bidirectional function. Additionally, an open-drain or open-
source function can be developed by resetting or setting the appropriate data bit and
using the data direction bit as the programmed data value.
After a reset or power-on, these bits will be set to a binary one, enabling the I/O as
an input with weak pull-up.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
12h: I/O Port 2 Data Direction (DDP2)
13h: I/O Port 3 Data Direction (DDP3)
Register Name:DDP2
Address:12h
Reset Value:1111_1111b
DescriptionI/O Port 2 Data Direction
76543210Data Direction
Bit(s)Bit LabelAccessDescription7:0DDP0.7-0R/WData Direction
These bits determine the direction of the data flow through the I/O pin.
To enable the respective I/O pin as an input, set the appropriate bit. To enable the
respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individ-
ually configured as a true bidirectional function. Additionally, an open-drain or open-
source function can be developed by resetting or setting the appropriate data bit and
using the data direction bit as the programmed data value.
After a reset or power-on, these bits will be set to a binary one, enabling the I/O as
an input with weak pull-up.
Register Name:DDP3
Address:13h
Reset Value:1111_1111b
DescriptionI/O Port 3 Data Direction
76543210Data Direction
Bit(s)Bit LabelAccessDescription7:0DDP0.7-0R/WData Direction
These bits determine the direction of the data flow through the I/O pin.
To enable the respective I/O pin as an input, set the appropriate bit. To enable the
respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individ-
ually configured as a true bidirectional function. Additionally, an open-drain or open-
source function can be developed by resetting or setting the appropriate data bit and
using the data direction bit as the programmed data value.
After a reset or power-on, these bits will be set to a binary one, enabling the I/O as
an input with weak pull-up.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
14h: I/O Port 4 Data Direction (DDP4)
Register Name:DDP4
Address:14h
Reset Value:1111_1111b
DescriptionI/O Port 4 Data Direction
76543210Data Direction
Bit(s)Bit LabelAccessDescription7:0DDP0.7-0R/WData Direction
These bits determine the direction of the data flow through the I/O pin.
To enable the respective I/O pin as an input, set the appropriate bit. To enable the
respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individ-
ually configured as a true bidirectional function. Additionally, an open-drain or open-
source function can be developed by resetting or setting the appropriate data bit and
using the data direction bit as the programmed data value.
After a reset or power-on, these bits will be set to a binary one, enabling the I/O as
an input with weak pull-up.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
20h: Port Bypass Control 0 (PBC0)
Register Name:PBC0
Address:20h
Reset Value:00XX_XX1Xb
DescriptionPort Bypass Control 0
76543210Port Bypass
Control Ena-
ble
Signal
Detected
Interrupt Ena-
ble
Force
Bypass
Signal
Detected
Bit(s)Bit LabelAccessDescriptionPBCENR/WPort Bypass Control Enable
When this bit is set, P3.1 and P3.0 are automatically configured to provide a Force
Bypass output pin and a Signal Detected input pin. Any other configuration which
may have previously been enabled through other control registers will be overrid-
den. When this bit is reset, the remaining bits in this register have no effect on the
operation of P3.1 and P3.0.SDIENR/WSignal Detected Interrupt Enable
When this bit is set, the SD input will be enabled to generate an interrupt if a transi-
tion occurs on the pin. If a transition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, transitions on the signal detected input will not generate an interrupt con-
dition.FBR/W Force Bypass
This bit controls the P3.1 I/O pin which is configured as a totem pole output by set-
ting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU
function is not enabled and the port bypass circuit is in normal mode. When this bit is
reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port
bypass circuit is in bypass mode. This register bit is automatically cleared when the
synchronized and filtered P3.0 input is low which results in a maximum latency of
400 nanoseconds from detection of the loss of a high speed signal to the deasser-
tion of the P3.1 output.
NOTE:Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it
is possible to define the default state of the force bypass function through the use
of an external pull-down resistor. The default state of the I/O can be determined
by reading this register since the read value of the register bits are always avail-
able through an input synchronizer and filter. Once the default state is deter-
mined, a write to the FB bit of this register with the default values as well as
setting the PBCEN bit ensures that the port bypass control functions have been
enabled correctly. Additional writes to this register can enable or disable the
force bypass functions at any time as long as the SD input remains high.SDR/WSignal Detected
When the PBCEN bit is set, this bit becomes a read-only indication of the P3.0 I/O
pin which has been connected to the signal detected output of a PBC/CRU/SDU
function. If this bit is set, a high speed signal has been detected by the signal detect
unit. If this bit is reset, a high speed signal has not been detected by the signal
detect unit.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
21h: Port Bypass Control 1 (PBC1)
Register Name:PBC1
Address:21h
Reset Value:00XX_XX1Xb
DescriptionPort Bypass Control 1
76543210Port Bypass
Control Ena-
ble
Signal
Detected
Interrupt Ena-
ble
Force
Bypass
Signal
Detected
Bit(s)Bit LabelAccessDescriptionPBCENR/WPort Bypass Control Enable
When this bit is set, P3.3 and P3.2 are automatically configured to provide a Force
Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins
which may have previously been enabled through other control registers will be
overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit
Control Registers). When this bit is reset, the remaining bits in this register have no
effect on the operation of P3.3 and P3.2.SDIENR/WSignal Detected Interrupt Enable
When this bit is set, the SD input will be enabled to generate an interrupt if a transi-
tion occurs on the pin. If a transition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, transitions on the signal detected input will not generate an interrupt con-
dition.FBR/W Force Bypass
This bit controls the P3.3 I/O pin, which is configured as a totem pole output by set-
ting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU
function is not enabled and the port bypass circuit is in normal mode. When this bit is
reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port
bypass circuit is in bypass mode. This register bit is automatically cleared when the
synchronized and filtered P3.2 input is low which results in a maximum latency of
400 nanosceonds from detection of the loss of a high speed signal to the de-asser-
tion of the P3.1 output.
NOTE:Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it
is possible to define the default state of the force bypass function through the use
of an external pull-down resistor. The default state of the I/O can be determined
by reading this register since the read value of the register bits are always avail-
able through an input synchronizer and filter. Once the default state is deter-
mined, a write to the FB bit of this register with the default values as well as
setting the PBCEN bit ensures that the port bypass control functions have been
enabled correctly. Additional writes to this register can enable or disable the
force bypass functions at any time as long as the SD input remains high.SDR/WSignal Detected
When the PBCEN bit is set, this bit becomes a read-only indication of the P3.2 I/O
pin which has been connected to the signal detected output of a PBC/CRU/SDU
function. If this bit is set, a high speed signal has been detected by the signal detect
unit. If this bit is reset, a high speed signal has not been detected by the signal
detect unit.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
22h: Port Bypass Control 2 (PBC2)
Register Name:PBC2
Address:22h
Reset Value:00XX_XX1Xb
DescriptionPort Bypass Control 2
76543210Port Bypass
Control Ena-
ble
Signal
Detected
Interrupt Ena-
ble
Force
Bypass
Signal
Detected
Bit(s)Bit LabelAccessDescriptionPBCENR/WPort Bypass Control Enable
When this bit is set, P3.5 and P3.4 are automatically configured to provide a Force
Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins
which may have previously been enabled through other control registers will be
overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit
Control Registers). When this bit is reset, the remaining bits in this register have no
effect on the operation of P3.5 and P3.4.SDIENR/WSignal Detected Interrupt Enable
When this bit is set, the SD input will be enabled to generate an interrupt if a transi-
tion occurs on the pin. If a transition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, transitions on the signal detected input will not generate an interrupt con-
dition.FBR/W Force Bypass
This bit controls the P3.5 I/O pin, which is configured as a totem pole output by set-
ting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU
function is not enabled and the port bypass circuit is in normal mode. When this bit is
reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port
bypass circuit is in bypass mode. This register bit is automatically cleared when the
synchronized and filtered P3.4 input is low which results in a maximum latency of
400 nanosceonds from detection of the loss of a high speed signal to the de-asser-
tion of the P3.1 output.
NOTE:Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it
is possible to define the default state of the force bypass function through the use
of an external pull-down resistor. The default state of the I/O can be determined
by reading this register since the read value of the register bits are always avail-
able through an input synchronizer and filter. Once the default state is deter-
mined, a write to the FB bit of this register with the default values as well as
setting the PBCEN bit ensures that the port bypass control functions have been
enabled correctly. Additional writes to this register can enable or disable the
force bypass functions at any time as long as the SD input remains high.SDR/WSignal Detected
When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O
pin which has been connected to the signal detected output of a PBC/CRU/SDU
function. If this bit is set, a high speed signal has been detected by the signal detect
unit. If this bit is reset, a high speed signal has not been detected by the signal
detect unit.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
23h: Port Bypass Control 3 (PBC3)
Register Name:PBC3
Address:23h
Reset Value:00XX_XX1Xb
DescriptionPort Bypass Control 3
76543210Port Bypass
Control Ena-
ble
Signal
Detected
Interrupt Ena-
ble
Force
Bypass
Signal
Detected
Bit(s)Bit LabelAccessDescriptionPBCENR/WPort Bypass Control Enable
When this bit is set, P3.7 and P3.6 are automatically configured to provide a Force
Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins
which may have previously been enabled through other control registers will be
overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit
Control Registers). When this bit is reset, the remaining bits in this register have no
effect on the operation of P3.7 and P3.6.SDIENR/WSignal Detected Interrupt Enable
When this bit is set, the SD input will be enabled to generate an interrupt if a transi-
tion occurs on the pin. If a transition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, transitions on the signal detected input will not generate an interrupt con-
dition.FBR/W Force Bypass
This bit controls the P3.7 I/O pin, which is configured as a totem pole output by set-
ting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU
function is not enabled and the port bypass circuit is in normal mode. When this bit is
reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port
bypass circuit is in bypass mode. This register bit is automatically cleared when the
synchronized and filtered P3.6 input is low which results in a maximum latency of
400 nanosceonds from detection of the loss of a high speed signal to the de-asser-
tion of the P3.1 output.
NOTE:Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it
is possible to define the default state of the force bypass function through the use
of an external pull-down resistor. The default state of the I/O can be determined
by reading this register since the read value of the register bits are always avail-
able through an input synchronizer and filter. Once the default state is deter-
mined, a write to the FB bit of this register with the default values as well as
setting the PBCEN bit ensures that the port bypass control functions have been
enabled correctly. Additional writes to this register can enable or disable the
force bypass functions at any time as long as the SD input remains high.SDR/WSignal Detected
When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O
pin which has been connected to the signal detected output of a PBC/CRU/SDU
function. If this bit is set, a high speed signal has been detected by the signal detect
unit. If this bit is reset, a high speed signal has not been detected by the signal
detect unit.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
24h: Port Bypass Control 4 (PBC4)
Register Name:PBC4
Address:24h
Reset Value:00XX_XX1Xb
DescriptionPort Bypass Control 4
76543210Port Bypass
Control Ena-
ble
Signal
Detected
Interrupt Ena-
ble
Force
Bypass
Signal
Detected
Bit(s)Bit LabelAccessDescriptionPBCENR/WPort Bypass Control Enable
When this bit is set, P4.1 and P4.0 are automatically configured to provide a Force
Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins
which may have previously been enabled through other control registers will be
overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit
Control Registers). When this bit is reset, the remaining bits in this register have no
effect on the operation of P4.1 and P4.0.SDIENR/WSignal Detected Interrupt Enable
When this bit is set, the SD input will be enabled to generate an interrupt if a transi-
tion occurs on the pin. If a transition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, transitions on the signal detected input will not generate an interrupt con-
dition.FBR/W Force Bypass
This bit controls the P4.1 I/O pin, which is configured as a totem pole output by set-
ting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU
function is not enabled and the port bypass circuit is in normal mode. When this bit is
reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port
bypass circuit is in bypass mode. This register bit is automatically cleared when the
synchronized and filtered P4.0 input is low which results in a maximum latency of
400 nanosceonds from detection of the loss of a high speed signal to the de-asser-
tion of the P3.1 output.
NOTE:Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it
is possible to define the default state of the force bypass function through the use
of an external pull-down resistor. The default state of the I/O can be determined
by reading this register since the read value of the register bits are always avail-
able through an input synchronizer and filter. Once the default state is deter-
mined, a write to the FB bit of this register with the default values as well as
setting the PBCEN bit ensures that the port bypass control functions have been
enabled correctly. Additional writes to this register can enable or disable the
force bypass functions at any time as long as the SD input remains high.SDR/WSignal Detected
When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O
pin which has been connected to the signal detected output of a PBC/CRU/SDU
function. If this bit is set, a high speed signal has been detected by the signal detect
unit. If this bit is reset, a high speed signal has not been detected by the signal
detect unit.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
25h: Port Bypass Control 5 (PBC5)
Register Name:PBC5
Address:25h
Reset Value:00XX_XX1Xb
DescriptionPort Bypass Control 5
76543210Port Bypass
Control Ena-
ble
Signal
Detected
Interrupt Ena-
ble
Force
Bypass
Signal
Detected
Bit(s)Bit LabelAccessDescriptionPBCENR/WPort Bypass Control Enable
When this bit is set, P4.3 and P4.2 are automatically configured to provide a Force
Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins
which may have previously been enabled through other control registers will be
overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit
Control Registers). When this bit is reset, the remaining bits in this register have no
effect on the operation of P4.3 and P4.2.SDIENR/WSignal Detected Interrupt Enable
When this bit is set, the SD input will be enabled to generate an interrupt if a transi-
tion occurs on the pin. If a transition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, transitions on the signal detected input will not generate an interrupt con-
dition.FBR/W Force Bypass
This bit controls the P4.3 I/O pin, which is configured as a totem pole output by set-
ting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU
function is not enabled and the port bypass circuit is in normal mode. When this bit is
reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port
bypass circuit is in bypass mode. This register bit is automatically cleared when the
synchronized and filtered P4.2 input is low which results in a maximum latency of
400 nanosceonds from detection of the loss of a high speed signal to the de-asser-
tion of the P3.1 output.
NOTE:Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it
is possible to define the default state of the force bypass function through the use
of an external pull-down resistor. The default state of the I/O can be determined
by reading this register since the read value of the register bits are always avail-
able through an input synchronizer and filter. Once the default state is deter-
mined, a write to the FB bit of this register with the default values as well as
setting the PBCEN bit ensures that the port bypass control functions have been
enabled correctly. Additional writes to this register can enable or disable the
force bypass functions at any time as long as the SD input remains high.SDR/WSignal Detected
When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O
pin which has been connected to the signal detected output of a PBC/CRU/SDU
function. If this bit is set, a high speed signal has been detected by the signal detect
unit. If this bit is reset, a high speed signal has not been detected by the signal
detect unit.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
26h: Port Bypass Control 6 (PBC6)
Register Name:PBC6
Address:26h
Reset Value:00XX_XX1Xb
DescriptionPort Bypass Control 6
76543210Port Bypass
Control Ena-
ble
Signal
Detected
Interrupt Ena-
ble
Force
Bypass
Signal
Detected
Bit(s)Bit LabelAccessDescriptionPBCENR/WPort Bypass Control Enable
When this bit is set, P4.5 and P4.4 are automatically configured to provide a Force
Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins
which may have previously been enabled through other control registers will be
overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit
Control Registers). When this bit is reset, the remaining bits in this register have no
effect on the operation of P4.5 and P4.4.SDIENR/WSignal Detected Interrupt Enable
When this bit is set, the SD input will be enabled to generate an interrupt if a transi-
tion occurs on the pin. If a transition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, transitions on the signal detected input will not generate an interrupt con-
dition.FBR/W Force Bypass
This bit controls the P4.5 I/O pin, which is configured as a totem pole output by set-
ting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU
function is not enabled and the port bypass circuit is in normal mode. When this bit is
reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port
bypass circuit is in bypass mode. This register bit is automatically cleared when the
synchronized and filtered P4.4 input is low which results in a maximum latency of
400 nanosceonds from detection of the loss of a high speed signal to the de-asser-
tion of the P3.1 output.
NOTE:Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it
is possible to define the default state of the force bypass function through the use
of an external pull-down resistor. The default state of the I/O can be determined
by reading this register since the read value of the register bits are always avail-
able through an input synchronizer and filter. Once the default state is deter-
mined, a write to the FB bit of this register with the default values as well as
setting the PBCEN bit ensures that the port bypass control functions have been
enabled correctly. Additional writes to this register can enable or disable the
force bypass functions at any time as long as the SD input remains high.SDR/WSignal Detected
When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O
pin which has been connected to the signal detected output of a PBC/CRU/SDU
function. If this bit is set, a high speed signal has been detected by the signal detect
unit. If this bit is reset, a high speed signal has not been detected by the signal
detect unit.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
27h: Port Bypass Control 7 (PBC7)
Register Name:PBC7
Address:27h
Reset Value:00XX_XX1Xb
DescriptionPort Bypass Control 7
76543210Port Bypass
Control Ena-
ble
Signal
Detected
Interrupt Ena-
ble
Force
Bypass
Signal
Detected
Bit(s)Bit LabelAccessDescriptionPBCENR/WPort Bypass Control Enable
When this bit is set, P4.7 and P4.6 are automatically configured to provide a Force
Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins
which may have previously been enabled through other control registers will be
overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit
Control Registers). When this bit is reset, the remaining bits in this register have no
effect on the operation of P4.7 and P4.6.SDIENR/WSignal Detected Interrupt Enable
When this bit is set, the SD input will be enabled to generate an interrupt if a transi-
tion occurs on the pin. If a transition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, transitions on the signal detected input will not generate an interrupt con-
dition.FBR/W Force Bypass
This bit controls the P4.7 I/O pin, which is configured as a totem pole output by set-
ting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU
function is not enabled and the port bypass circuit is in normal mode. When this bit is
reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port
bypass circuit is in bypass mode. This register bit is automatically cleared when the
synchronized and filtered P4.6 input is low which results in a maximum latency of
400 nanosceonds from detection of the loss of a high speed signal to the de-asser-
tion of the P3.1 output.
NOTE:Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it
is possible to define the default state of the force bypass function through the use
of an external pull-down resistor. The default state of the I/O can be determined
by reading this register since the read value of the register bits are always avail-
able through an input synchronizer and filter. Once the default state is deter-
mined, a write to the FB bit of this register with the default values as well as
setting the PBCEN bit ensures that the port bypass control functions have been
enabled correctly. Additional writes to this register can enable or disable the
force bypass functions at any time as long as the SD input remains high.SDR/WSignal Detected
When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O
pin which has been connected to the signal detected output of a PBC/CRU/SDU
function. If this bit is set, a high speed signal has been detected by the signal detect
unit. If this bit is reset, a high speed signal has not been detected by the signal
detect unit.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
30h: Fan Speed Control 0 Register (FSC0)
Register Name:FSC0
Address:30h
Reset Value:00XX_XX00b
DescriptionFan Speed Control 0.
This register affects pin P2.4.
76543210Fan Speed
Control Ena-
ble
Fan Speed
Interrupt Ena-
ble
Fan Divisor 1Fan Divisor 0
Bit(s)Bit LabelAccessDescriptionFSCENR/WFan Speed Control Enable
When this bit is set, P2.4 is automatically configured to provide a fan speed monitor-
ing input. Configurations for this I/O pin which may have previously been enabled
through other control registers will be overridden except for the bypass select func-
tion (bits 6 and 5 of the appropriate Bit Control Registers). If the appropriate bypass
bits have been set, the odd numbered fan speed input pins (P2.1, P2.3, P2.5, or
P2.7) will be configured as outputs. When this bit is reset, the remaining bits in this
register have no effect on the operation of P2.4.
When enabled as a fan speed monitoring input, pulses from the fan tachometer out-
put gate an internal 20KHz clock into an eight-bit counter. A divisor value stored in
bits one and zero of this register allow the user to select one of four nominal RPM
values based on fan tachometer outputs which pulse twice per revolution. The
FSCC0 register provides the user with an accurate binary fan speed count value
which can be used to determine the current RPM value of the fan. Incoming pulses
are filtered and conditioned to accommodate the slow rise and fall times typical of
fan tachometer outputs. The maximum input signal is limited to a range of VSS to
VDD. If this input is supplied from a fan tachometer output which exceeds this range,
external components will be required to limit the signal to an acceptable range. FSIENR/WFan Speed Interrupt Enable
When this bit is set, the P2.4 input will be enabled to generate an interrupt if the
eight bit counter value is greater than or equal to the count overflow value loaded
into the FSCO0 register. If the condition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, the fan speed monitoring logic will not generate an interrupt condition.
1:0FD1-0R/WFan Divisor
These two bits determine the divisor value used to determine the correct range of
RPM values supplied to the eight-bit fan speed counter. Table 4-3 describes the
available divisor values.
The decimal count value can be calculated using the following equation:
Decimal-Count-Value = (1,200,000)/(RPM X Divisor)
Any nominal RPM value can be used in the above equation along with the appropri-
ate divisor as long as the maximum non-failure count value does not exceed the lim-
its of an eight-bit counter. Typical applications may consider 60% to 70% of normal
RPM a fan failure which would result in a decimal count value of 250(FAh) and
214(D6h) respectively at the above stated RPM values.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
Table 4-3:Fan Divisor
FD1FD0DivisorNominal RPMDecimal Count Value018000150(96h)124000150(96h)042000150(96h)181000150(96h)
Control RegistersSSC050-01
Control Register DefinitionData Sheet
31h: Fan Speed Count Overflow 0 (FSCO0, R/W)
Register Name:FSCO0
Address:31h
Reset Value:0000_0000b
DescriptionFan Speed Count Overflow 0.
This register affects pin P2.4
76543210Fan Speed Count Overflow
Bit(s)Bit LabelAccessDescriptionFSCO7-0 R/WFan Speed Count Overflow
These eight bits are compared to the eight-bit fan speed counter. If the counter
exceeds this value, an interrupt will be generated. This register should be loaded
prior to setting the Fan Speed Control Enable (FSCEN) bit in the FSC0 register to
avoid generating unintentional interrupts. The overflow count value can be deter-
mined using the following equation where FF% is equal to the percentage of nominal
RPM which constitutes a fan failure:
Decimal-Overflow-Count-Value = (1,200,000)/(RPM X Divisor X FF%)
Based on the above equation, a divisor of 8 and a detected fan failure at 70% of
nominal RPM, the fan speed monitoring logic is capable of supporting a low end
nominal RPM of 850. High end RPM values are basically unlimited but counter reso-
lution will be diminished above 8000 RPM.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
32h: Fan Speed Current Count 0 (FSCC0)
Register Name:FSCC0
Address:32h
Reset Value:0000_0000b
DescriptionFan Speed Current Count 0.
This register affects pin P P2.4.
76543210Fan Speed Current Count
Bit(s)Bit LabelAccessDescriptionFSCO7-0 RThese eight bits, when enabled by setting the FSCEN bit in the FSC0 register pro-
vide the user with an accurate binary fan speed count value which can be used to
determine the current RPM value of the fan. A minimum of one complete revolution
of the fan is required to generate an accurate fan speed count value. The following
equation can be used to determine the current RPM value of the fan:
RPM = (1,200,000)/(Decimal-Count-Value X Divisor)
When the result of a read of this register is 00h, an accurate fan speed count value
has not been generated indicating that the fan has not completed a minimum of one
revolution. When the result of a read of this register is FFh, the fan is rotating very
slowly or there are no tachometer pulses present. When operating in a polled mode
with the FSIEN bit reset in the FSC0 register, this register will automatically update
with an accurate fan speed count once per revolution of the fan. When operating in
an interrupt mode with the FSIEN bit set in the FSC0 register, this register will auto-
matically update with an accurate fan speed count once per revolution of the fan until
an interrupt is generated. Once the interrupt is generated, the value will remain sta-
ble until the interrupt is cleared. When the interrupt is cleared, this register will also
be cleared indicating that a valid RPM value is in the process of being generated.
Control RegistersSSC050-01
Control Register DefinitionData Sheet
34h: Fan Speed Control 1 (FSC1)
Register Name:FSC1
Address:34h
Reset Value:00XX_XX00b
DescriptionFan Speed Control 1.
This register affects pin P2.5
76543210Fan Speed
Control Ena-
ble
Fan Speed
Interrupt Ena-
ble
Fan Divisor 1Fan Divisor 0
Bit(s)Bit LabelAccessDescriptionFSCENR/WFan Speed Control Enable
When this bit is set, P2.5 is automatically configured to provide a fan speed monitor-
ing input. Configurations for this I/O pin which may have previously been enabled
through other control registers will be overridden except for the bypass select func-
tion (bits 6 and 5 of the appropriate Bit Control Registers). If the appropriate bypass
bits have been set, the odd numbered fan speed input pins (P1.1, P1.3, P1.5, P1.7,
P2.1, P2.3, P2.5 or P2.7) will be configured as outputs. When this bit is reset, the
remaining bits in this register have no effect on the operation of P2.5.
When enabled as a fan speed monitoring input, pulses from the fan tachometer out-
put gate an internal 20KHz clock into an eight-bit counter. A divisor value stored in
bits one and zero of this register allow the user to select one of four nominal RPM
values based on fan tachometer outputs which pulse twice per revolution. The
FSCC1 register provides the user with an accurate binary fan speed count value
which can be used to determine the current RPM value of the fan. Incoming pulses
are filtered and conditioned to accommodate the slow rise and fall times typical of
fan tachometer outputs. The maximum input signal is limited to a range of VSS to
VDD. If this input is supplied from a fan tachometer output which exceeds this range,
external components will be required to limit the signal to an acceptable range. FSIENR/WFan Speed Interrupt Enable
When this bit is set, the P2.5 input will be enabled to generate an interrupt if the
eight bit counter value is greater than or equal to the count overflow value loaded
into the FSCO1 register. If the condition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, the fan speed monitoring logic will not generate an interrupt condition.
1:0FD1-0R/WFan Divisor
These two bits determine the divisor value used to determine the correct range of
RPM values supplied to the eight-bit fan speed counter. Table 4-4 describes the
available divisor values:
The decimal count value can be calculated using the following equation:
Decimal-Count-Value = (1,200,000)/(RPM X Divisor)
Any nominal RPM value can be used in the above equation along with the appropri-
ate divisor as long as the maximum non-failure count value does not exceed the lim-
its of an eight-bit counter. Typical applications may consider 60% to 70% of normal
RPM a fan failure which would result in a decimal count value of 250 (FAh) and 214
(D6h) respectively at the above stated RPM values.
