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SRK2000DTRSTMN/a2030avaiSYNCHRONOUS RECTIFIER SMART DRIVER FOR LLC RESONANT CONVERTER


SRK2000DTR ,SYNCHRONOUS RECTIFIER SMART DRIVER FOR LLC RESONANT CONVERTERPin configurationSG SGN ND D 1 1 8 8 Vc Vcc cEN EN 2 2 7 7 GD GD1 1DV DVS S1 1 3 3 6 6 PG PGN ND DD ..
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SRK2000DTR
SYNCHRONOUS RECTIFIER SMART DRIVER FOR LLC RESONANT CONVERTER
August 2013 DocID17811 Rev 3 1/19
SRK2000

Synchronous rectifier smart driver for LLC resonant converters
Datasheet - production data
Features
Secondary-side synchronous rectifier
controller optimized for LLC resonant
converters Protection against current reversal Safe management of load transient, light load
and startup condition Intelligent automatic sleep mode at light load Dual gate driver for N-channel MOSFETs with
1 A source and 3.5 A sink drive current Operating voltage range 4.5 to 32 V Programmable UVLO with hysteresis 250 µA quiescent consumption Operating frequency up to 500 kHz Available in SO-8 package
Applications
All-in-one PC High-power AC-DC adapters 80+/85+ compliant ATX SMPS 90+/92+ compliant server SMPS Industrial SMPS
Description

The SRK2000 smart driver implements a control
scheme specific to secondary-side synchronous
rectification in LLC resonant converters that use
a transformer with center-tap secondary winding
for full-wave rectification.
It provides two high current gate drive outputs,
each capable of driving one or more N-channel
Power MOSFETs. Each gate driver is controlled
separately and an interlocking logic circuit
prevents the two synchronous rectifier MOSFETs
from conducting simultaneously.
The control scheme in this IC allows for each
synchronous rectifier to be switched on as the
corresponding half-winding starts conducting and
switched off as its current goes to zero. A unique
feature of this IC is its intelligent automatic sleep
mode. It allows the detection of a low-power
operating condition for the converter and puts the
IC into a low consumption sleep mode where gate
driving is stopped and quiescent consumption is
reduced. In this way, converter efficiency
improves at light load, where synchronous
rectification is no longer beneficial. The IC
automatically exits sleep mode and restarts
switching as it recognizes that the load for the
converter has increased.
A noticeable feature is the very low external
component count required.

Table 1. Device summary
Contents SRK2000
2/19 DocID17811 Rev 3
Contents Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.1 EN pin - pin function and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.1.1 Pull-up resistor configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.1.2 Resistor divider configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1.3 Remote on/off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2 Drain voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.3 Gate driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4 Intelligent automatic sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5 Protection against current reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.6 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DocID17811 Rev 3 3/19
SRK2000 Internal block diagram
1 Internal block diagram
Pin description SRK2000
4/19 DocID17811 Rev 3
2 Pin description
DocID17811 Rev 3 5/19
SRK2000 Pin description
Maximum ratings SRK2000
3 Maximum ratings


Typical application schematic
Table 3. Absolute maximum ratings
Table 4. Thermal data
DocID17811 Rev 3 7/19
SRK2000 Electrical characteristics
5 Electrical characteristics

TJ = -25 to 125 °C, VCC = 12 V, CGD1 = CGD2 = 4.7 nF, EN = VCC; unless otherwise
specified; typical values refer to TJ = 25 °C.
Table 5. Electrical characteristics
Electrical characteristics SRK2000
8/19 DocID17811 Rev 3 Parameters tracking each other. For VCC > 30 V IDVS1,2_b may be greater than 1 µA because of the possible current contribution of the internal clamp Zener (few tens of µA).
Table 5. Electrical characteristics (continued)
DocID17811 Rev 3 9/19
SRK2000 Application information
6 Application information
6.1 EN pin - pin function and usage

This pin can perform three different functions: it sets the threshold VDVS1,2_Off for the drain-
to-source voltage of either synchronous rectifier (SR) Power MOSFET to determine their
turn-off in each conduction cycle; it allows the user to program the UVLO thresholds of the
gate drivers and can be used as Enable (remote on/off control).
6.1.1 Pull-up resistor configuration
Application information SRK2000
10/19 DocID17811 Rev 3
As VCC exceeds VCCOn, the internal current sink IEN is switched off and the enable function
is activated. The voltage on the pin is then compared to an internal reference VEN_On set at
1.8 V: if this threshold is exceeded the gate drivers GD1 and GD2 are enabled and the SR
MOSFET is operated; otherwise, the device stays in an idle condition and the SR MOSFET
in the off state.
Using the pull-up resistor RP, the voltage on the EN pin rises as IEN is switched off and tends
to VCC, therefore exceeding VEN_On and enabling the operation of both SR MOSFETs.
Essentially, this results in enabling the gate-driving as VCC exceeds VCCOn and disabling it
as VCC falls below VCCOn. This configuration is thereby recommended when SR MOSFETs
are logic level types.
6.1.2 Resistor divider configuration
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