SPC56AP60L3 ,32-bit Power Architecture MCU for Automotive Chassis and Safety ApplicationsFeatures■ 64 MHz, single issue, 32-bit CPU core complex (e200z0h)LQFP100 LQFP144 ®14 x 14 mm– Compl ..
SPC6601ST6RG , N & P Pair Enhancement Mode MOSFET
SPC6602ST6RG , N & P Pair Enhancement Mode MOSFET
SPC714M , Mini Flat Photo Coupler
SPC-714M , Mini Flat Photo Coupler
SPC-814M , Mini Flat Photo Coupler
SST39VF040-90-4C-NH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040-90-4C-NH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040-90-4C-WH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040-90-4I-NH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040-90-4I-WH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF080-70-4C-EI , 8 Mbit / 16 Mbit (x8) Multi-Purpose Flash
SPC56AP60L3
32-bit Power Architecture MCU for Automotive Chassis and Safety Applications
September 2013 Doc ID 18340 Rev 5 1/105
SPC56AP60x, SPC56AP54x
SPC560P60x, SPC560P54x32-bit Power Architecture® based MCU with 1088 KB Flash memory
and 80 KB RAM for automotive chassis and safety applications
Datasheet − production data
Features 64 MHz, single issue, 32-bit CPU core complex
(e200z0h) Compliant with Power Architecture®
embedded category Variable Length Encoding (VLE) Memory organizazion Up to 1024 KB on-chip code Flash memory
with additional 64 KB for EEPROM
emulation (data flash), with ECC, with
erase/program controller Up to 80 KB on-chip SRAM with ECC Fail safe protection ECC protection on system SRAM and
Flash Safety port SWT with servicing sequence pseudo-
random generator Power management Non-maskable interrupt for both cores Fault collection and control unit (FCCU) Safe mode of system-on-chip (SoC) Register protection scheme Nexus® L2+ interface Single 3.3 V or 5 V supply for I/Os and ADC 2 on-platform peripherals set with 2 INTC 16-channel eDMA controller with multiple
transfer request sources General purpose I/Os (80 GPIO + 26 GPI on
LQFP144; 49 GPIO + 16 GPI on LQFP100) 2 general purpose eTimer units 6 timers, each with up/down count
capabilities 16-bit resolution, cascadable counters Quadrature decode with rotation direction
flag Double buffer input capture and output
compare Communications interfaces 2 LINFlex modules (LIN 2.1,
1 × Master/Slave, 1 × Master Only) 5 DSPI modules with automatic chip select
generation 2 FlexCAN interfaces (2.0B Active) with 32
message buffers 1 Safety port based on FlexCAN; usable as
third CAN when not used as safety port 1 FlexRay™ module (V2.1) with dual or
single channel, 64 message buffers and up
to 10 Mbit/s 2 CRC units with three contexts and 3
hardwired polynomials(CRC8,CRC32 and
CRC-16-CCITT) 10-bit A/D converter 27 input channels and pre-sampling feature Conversion time <1 µs including sampling
time at full precision Programmable cross triggering unit (CTU) 4 analog watchdog with interrupt capability On-chip CAN/UART Bootstrap loader with boot
assist module (BAM) Ambient temperature ranges: –40 to 125 °C or
–40 to 105°C
Table 1. Device summary
Contents SPC56xP54x, SPC56xP60x
2/105 Doc ID 18340 Rev 5
Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.1 High performance e200z0h core processor . . . . . . . . . . . . . . . . . . . . . . 13
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.3 Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.4 On-chip flash memory with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.5 On-chip SRAM with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.7 System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.8 Frequency modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . 16
1.5.9 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.10 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.11 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.12 System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.13 Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.14 Fault collection and control unit (FCCU) . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.15 System integration unit (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.16 Boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.17 Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.18 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.19 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.20 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.21 Serial communication interface module (LINFlex) . . . . . . . . . . . . . . . . . 21
1.5.22 Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 22
1.5.23 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5.24 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5.25 Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5.26 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5.27 Nexus development interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5.28 IEEE 1149.1 (JTAG) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPC56xP54x, SPC56xP60x Contents
Doc ID 18340 Rev 5 3/105
1.5.29 On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 27
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.1 Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.3 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.5.1 General notes for specifications at maximum junction temperature . . . 56
3.6 Electromagnetic interference (EMI) characteristics . . . . . . . . . . . . . . . . . 58
3.7 Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . . 58
3.8 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 58
3.8.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 58
3.8.2 Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60
3.9 Power Up/Down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.10 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.10.1 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.11 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.11.1 DC electrical characteristics (5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.11.2 DC electrical characteristics (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.11.3 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.12 Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.14 16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 74
3.15 Analog-to-Digital converter (ADC) electrical characteristics . . . . . . . . . . . 74
3.15.1 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.15.2 ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.16 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Contents SPC56xP54x, SPC56xP60x
4/105 Doc ID 18340 Rev 5
3.17 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.17.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.18 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.18.1 RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.18.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.18.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.18.4 External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.18.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2.1 LQFP144 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2.2 LQFP100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SPC56xP54x, SPC56xP60x List of tables
Doc ID 18340 Rev 5 5/105
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. SPC56xP54/60 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. SPC56xP54/60 device configuration difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. SPC56xP54/60 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6. System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 10. Recommended operating conditions (5.0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 11. Recommended operating conditions (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 12. Thermal characteristics for 144-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 13. Thermal characteristics for 100-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 14. EMI testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 15. ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 16. Approved NPN ballast components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 17. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 18. Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 19. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 20. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . . . . . . . . . . 64
Table 21. Supply current (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 22. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . . . . . . . . . . 67
Table 23. Supply current (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 24. Peripherals supply current (5 V and 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 25. I/O supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 26. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 27. Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . 72
Table 28. Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . 72
Table 29. Input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 30. PLLMRFM electrical specifications
(VDDPLL = 1.08 V to 1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH) . . . . . . . . . . . . . . . . . . . 73
Table 31. 16 MHz RC oscillator electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 32. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 33. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 34. Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 35. Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 36. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 37. RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 38. JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 39. Nexus debug port timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 40. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 41. DSPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 42. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 43. LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 44. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
List of figures SPC56xP54x, SPC56xP60x
6/105 Doc ID 18340 Rev 5
List of figures
Figure 1. SPC56xP54/60 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2. LQFP176 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3. LQFP144 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 4. LQFP100 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5. Power supplies constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 6. Independent ADC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 7. Power supplies constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 8. Independent ADC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 9. Voltage regulator configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10. Power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 11. Power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 12. Brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 13. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 14. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 15. ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 16. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 17. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 18. Transient behavior during sampling phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 19. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 20. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 21. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 22. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 23. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 24. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 25. Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 26. Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 27. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 28. External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 29. DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 30. DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 31. DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 32. DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 33. DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 34. DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 35. DSPI modified transfer format timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 36. DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 37. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 38. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 39. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 40. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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1 Introduction
1.1 Document overview
This document provides electrical specifications, pin assignments, and package diagrams
for the SPC56xP54/60 series of microcontroller units (MCUs). It also describes the device
features and highlights important electrical and physical characteristics. For functional
characteristics, refer to the device reference manual.
1.2 Description
This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest
achievement in integrated automotive application controllers. It belongs to an expanding
range of automotive-focused products designed to address chassis applications specifically
the airbag application.
This family is one of a series of next-generation integrated automotive microcontrollers
based on the Power Architecture technology.
The advanced and cost-efficient host processor core of this automotive controller family
complies with the Power Architecture embedded category. It operates up to 64 MHz and
offers high performance processing optimized for low power consumption. It capitalizes on
the available development infrastructure of current Power Architecture devices and is
supported with software drivers, operating systems and configuration code to assist with
users implementations.
1.3 Device comparison
Table 2 provides a summary of different members of the SPC56xP54/60 family and their
features—relative to Full-featured version—to enable a comparison among the family
members and an understanding of the range of functionality offered within this family.
Table 2. SPC56xP54/60 device comparison
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SPC56xP54/60 is present on the market in two different options enabling different features:
Full-featured, and Airbag configuration. Table 3 shows the main differences between the
two versions. Each FlexCAN module has 32 message buffers. One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s. Enhanced FCCU version Same amount of ADC channels as on SPC560P44/50 not considering the internally connected ones. 26 channels on
LQFP144 and 16 channels on LQFP100. Increased number of CS for DSPI_1 Upgraded specification with addition of 8-bits polynomial (CRC-8 VDA CAN) support and 3rd context Improved debugging capability with data trace capability and increased Nexus throughput available on emulation package 3.3 V range and 5 V range correspond to different orderable parts. Software development package only. Not available for production.
Table 2. SPC56xP54/60 device comparison (continued)
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1.4 Block diagram
Figure 1 shows a top-level block diagram of the SPC56xP54/60 MCU. Table 4 summarizes
the functions of the blocks.
Table 3. SPC56xP54/60 device configuration difference
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Figure 1. SPC56xP54/60 block diagram
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Table 4. SPC56xP54/60 series block summary
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Table 4. SPC56xP54/60 series block summary (continued)
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1.5 Feature details
1.5.1 High performance e200z0h core processor
The e200z0h Power Architecture core provides the following features: High performance e200z0 core processor for managing peripherals and interrupts Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU Harvard architecture Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions Results in smaller code size footprint Minimizes impact on performance Branch processing acceleration using lookahead instruction buffer Load/store unit 1-cycle load latency Misaligned access support No load-to-use pipeline bubbles Thirty-two 32-bit general purpose registers (GPRs) Separate instruction bus and load/store bus Harvard architecture Hardware vectored interrupt support Reservation instructions for implementing read-modify-write constructs Long cycle time instructions, except for guarded loads, do not increase interrupt
latency Extensive system development support through Nexus debug port Non maskable Interrupt support
1.5.2 Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between six
master ports and six slave ports. The crossbar supports a 32-bit address bus width and a
32-bit data bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic selects the higher priority master and grant it ownership of the slave port. All
other masters requesting that slave port are stalled until the higher priority master
completes its transactions. Requesting masters are treated with equal priority and will be
granted access to a slave port in round-robin fashion, based upon the ID of the last master
to be granted access.
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The crossbar provides the following features: 6 master ports: 2 e200z0 core complex Instruction ports 2 e200z0 core complex Load/Store Data ports
–eDMA
–FlexRay 6 slave ports: 2 Flash memory (code flash and data flash) 2 SRAM (48 KB + 32 KB)
–2 PBRIDGE 32-bit internal address, 32-bit internal data paths Fixed Priority Arbitration based on Port Master Temporary dynamic priority elevation of masters
1.5.3 Enhanced direct memory access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels. This implementation is utilized to minimize the
overall block size.
The eDMA module provides the following features: 16 channels support independent 8, 16 or 32-bit single value or block transfers Supports variable sized queues and circular queues Source and destination address registers are independently configured to post-
increment or remain constant Each transfer is initiated by a peripheral, CPU, or eDMA channel request Each eDMA channel can optionally send an interrupt request to the CPU on completion
of a single value or block transfer DMA transfers possible between system memories, DSPIs, ADC, eTimer and CTU Programmable DMA Channel Multiplexer for assignment of any DMA source to any
available DMA channel with up to 30 potential request sources eDMA abort operation through software
1.5.4 On-chip flash memory with ECC
The SPC56xP54/60 provides up to 1024 KB of programmable, non-volatile, flash memory.
The non-volatile memory (NVM) can be used for instruction and/or data storage. The flash
memory module interfaces the system bus to a dedicated flash memory array controller. It
supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to
flash memory. The module contains a four-entry, 4x128-bit prefetch buffers. Prefetch buffer
hits allow no-wait responses. Normal flash memory array accesses are registered and are
forwarded to the system bus on the following cycle, incurring 2 wait states.
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The flash memory module provides the following features: Up to 1024 KB flash memory 14 blocks (2×16 KB+ 2×32 KB+ 2×16 KB+ 2×64 KB+ 6×128 KB) code flash 4 blocks (16 KB+16 KB+16 KB+16 KB) data flash Full Read While Write (RWW) capability between code and data flash Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch
buffers can be configured to prefetch code or data or both) Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page
buffer miss at 64 MHz Hardware managed flash memory writes handled by 32-bit RISC Krypton engine Hardware and software configurable read and write access protections on a per-master
basis. Configurable access timing allowing use in a wide range of system frequencies. Multiple-mapping support and mapping-based block access timing (0–31 additional
cycles) allowing use for emulation of other memory types. Software programmable block program/erase restriction control. Erase of selected block(s) Read page size of 128 bits (4 words) 64-bit ECC with single-bit correction, double-bit detection for data integrity Embedded hardware program and erase algorithm Erase suspend, program suspend and erase-suspended program Censorship protection scheme to prevent flash memory content visibility Hardware support for EEPROM emulation
1.5.5 On-chip SRAM with ECC
The SPC56xP54/60 SRAM module provides a general-purpose memory of up to 80 KB.
The SRAM module provides the following features: Supports read/write accesses mapped to the SRAM memory from any master Up to 80 KB general purpose RAM 2 blocks (48 KB+32 KB) Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of
memory Typical SRAM access time: 0 wait state for reads and 32-bit writes; 1 wait state for 8-
and 16-bit writes if back to back with a read to same memory block
1.5.6 Interrupt controller (INTC)
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from
the peripheral to when the processor is executing the interrupt service routine (ISR) has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR needs to be executed. It also provides an ample number
of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
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allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the resource can not preempt each other.
The INTC provides the following features: Unique 9-bit vector for each separate interrupt source 8 software triggerable interrupt sources 16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source Ability to modify the ISR or task priority. Modifying the priority can be used to implement the Priority Ceiling Protocol for
accessing shared resources. 2 external high priority interrupts directly accessing the main core and IOP critical
interrupt mechanism
The INTC module is replicated for each processor.
1.5.7 System clocks and clock generation
The following list summarizes the system clock and clock generation on the SPC56xP54/60: Lock detect circuitry continuously monitors lock status Loss of clock (LOC) detection for PLL outputs Programmable output clock divider (÷1, ÷2, ÷4, ÷8) Programmable output clock divider (÷1, ÷2, ÷3 to ÷256) eTimer module running at the same frequency as the e200z0h core On-chip oscillator with automatic level control Internal 16 MHz RC oscillator for rapid start-up and safe mode Supports frequency trimming by user application
1.5.8 Frequency modulated phase-locked loop (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz
input clock. Further, the FMPLL supports programmable frequency modulation of the
system clock. The FMPLL multiplication factor, output clock divider ratio are all software
configurable.
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The FMPLL has the following major features: Input clock frequency from 4 MHz to 40 MHz Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz Reduced frequency divider (RFD) for reduced frequency operation without forcing the
PLL to relock Modulation enabled/disabled through software Triangle wave modulation Programmable modulation depth (±0.25% to ±4% deviation from center frequency) Programmable modulation frequency dependent on reference frequency Self-clocked mode (SCM) operation
1.5.9 Main oscillator
The main oscillator provides these features: Input frequency range 4 MHz to 40 MHz Crystal input mode or Oscillator input mode PLL reference
1.5.10 Internal RC oscillator
This device has an RC ladder phase-shift oscillator. The architecture uses constant current
charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap
reference voltage.
The RC Oscillator provides these features: Nominal frequency 16 MHz ±6% variation over voltage and temperature after process trim Clock output of the RC oscillator serves as system clock source in case loss of lock or
loss of clock is detected by the PLL RC oscillator is used as the default system clock during startup
1.5.11 Periodic interrupt timer (PIT)
The PIT module implements these features: Up to four general purpose interrupt timers 32-bit counter resolution Clocked by system clock frequency Each channel can be used as trigger for a DMA request
1.5.12 System timer module (STM)
The STM module implements these features: 32-bit up counter with 8-bit prescaler Four 32-bit compare channels Independent interrupt source for each channel Counter can be stopped in debug mode
The STM module is replicated for each processor.
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1.5.13 Software watchdog timer (SWT)
The SWT has the following features: Fault tolerant output Safe internal RC oscillator as reference clock Windowed watchdog Program flow control monitor with 16-bit pseudorandom key generation
The SWT module is replicated for each processor.
1.5.14 Fault collection and control unit (FCCU)
The FCCU provides an independent fault reporting mechanism even if the CPU is exhibiting
unstable behaviors. The FCCU module has the following features: Redundant collection of hardware checker results Redundant collection of error information and latch of faults from critical modules on
the device Collection of self-test results Configurable and graded fault control Internal reactions (no internal reaction, IRQ) External reaction (failure is reported to the external/surrounding system via
configurable output pins)
1.5.15 System integration unit (SIUL)
The SPC56xP54/60 SIUL controls MCU pad configuration, external interrupts, general
purpose I/O (GPIO) pin configuration, and internal peripheral multiplexing.
The pad configuration block controls the static electrical characteristics of I/O pins. The
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.
The SIUL provides the following features: Centralized general purpose input output (GPIO) control of input/output pins and
analog input-only pads (package dependent) All GPIO pins can be independently configured to support pull-up, pull down, or no pull Reading and writing to GPIO supported both as individual pins and 16-bit wide ports All peripheral pins (except ADC channels) can be alternatively configured as both
general purpose input or output pins ADC channels support alternative configuration as general purpose inputs Direct readback of the pin value is supported on all pins through the SIU Configurable digital input filter that can be applied to some general purpose input pins
for noise elimination Up to 4 internal functions can be multiplexed onto one pin
1.5.16 Boot and censorship
Different booting modes are available in the SPC56xP54/60: From internal flash memory Via a serial link
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The default booting scheme is the one which uses the internal flash memory (an internal
pull-down is used to select this mode). The alternate option allows the user to boot via
FlexCAN or LINFlex (using the boot assist module software).
A censorship scheme is provided to protect the contents of the flash memory and offer
increased security for the entire device.
A password mechanism is designed to grant the legitimate user access to the non-volatile
memory.
Boot assist module (BAM)
The BAM is a block of read-only one-time programmed memory and is identical for all
SPC56xP54/60 devices that are based on the e200z0h core. The BAM program is executed
every time the device is powered on if the alternate boot mode has been selected by the
user.
The BAM provides the following features: Serial bootloading via FlexCAN or LINFlex. BAM can accept a password via the used serial communication channel to grant the
legitimate user access to the non-volatile memory.
1.5.17 Error correction status module (ECSM)
The ECSM on this device features the following: Platform configuration and revision ECC error reporting for flash memory and SRAM ECC error injection for SRAM
The ECSM module is replicated for each processor.
1.5.18 FlexCAN
The FlexCAN module is a communication controller implementing the CAN protocol
according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-
time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness
and required bandwidth. FlexCAN module contains 32 message buffers.
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The FlexCAN module provides the following features: Full implementation of the CAN protocol specification, Version 2.0B Standard data and remote frames Extended data and remote frames 0 to 8 bytes data length Programmable bit rate as fast as 1 Mbit/s 32 message buffers of 0 to 8 bytes data length Each message buffer configurable as Rx or Tx, all supporting standard and extended
messages Programmable loop-back mode supporting self-test operation 3 programmable mask registers Programmable transmit-first scheme: lowest ID or lowest buffer number Time stamp based on 16-bit free-running timer Global network time, synchronized by a specific message Maskable interrupts Independent of the transmission medium (an external transceiver is assumed) High immunity to EMI Short latency time due to an arbitration scheme for high-priority messages Transmit features Supports configuration of multiple mailboxes to form message queues of scalable
depth Arbitration scheme according to message ID or message buffer number Internal arbitration to guarantee no inner or outer priority inversion Transmit abort procedure and notification Receive features Individual programmable filters for each mailbox 8 mailboxes configurable as a six-entry receive FIFO 8 programmable acceptance filters for receive FIFO Programmable clock source System clock Direct oscillator clock to avoid PLL jitter
1.5.19 Safety port (FlexCAN)
The SPC56xP54/60 MCU has a second CAN controller synthesized to run at high bit rates
to be used as a safety port. The CAN module of the safety port provides the following
features: Identical to the FlexCAN module Bit rate as fast as 7.5 Mb at 60 MHz CPU clock using direct connection between CAN
modules (no physical transceiver required) 32 Message buffers of 0 to 8 bytes data length Can be used as a third independent CAN module
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1.5.20 FlexRay
The FlexRay module provides the following features: Full implementation of FlexRay Protocol Specification 2.1 64 configurable message buffers can be handled Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate Message buffers configurable as Tx, Rx or RxFIFO Message buffer size configurable Message filtering for all message buffers based on FrameID, cycle count and message Programmable acceptance filters for RxFIFO message buffers
1.5.21 Serial communication interface module (LINFlex)
The LINFlex on the SPC56xP54/60 features the following: Supports LIN Master mode (on both modules), LIN Slave mode (on one module) and
UART mode LIN state machine compliant to LIN1.3, 2.0, and 2.1 Specifications Handles LIN frame transmission and reception without CPU intervention LIN features Autonomous LIN frame handling Message buffer to store Identifier and up to 8 data bytes Supports message length as long as 64 bytes Detection and flagging of LIN errors: Sync field; Delimiter; ID parity; Bit; Framing;
Checksum and Time-out errors Classic or extended checksum calculation Configurable Break duration as long as 36-bit times Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional) Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection Interrupt-driven operation with 16 interrupt sources LIN slave mode features Autonomous LIN header handling Autonomous LIN response handling UART mode Full-duplex operation Standard non return-to-zero (NRZ) mark/space format Data buffers with 4-byte receive, 4-byte transmit Configurable word length (8-bit or 9-bit words) Error detection and flagging Parity, Noise and Framing errors Interrupt-driven operation with four interrupt sources Separate transmitter and receiver CPU interrupt sources 16-bit programmable baud-rate modulus counter and 16-bit fractional 2 receiver wake-up methods
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1.5.22 Deserial serial peripheral interface (DSPI)
The deserial serial peripheral interface (DSPI) module provides a synchronous serial
interface for communication between the SPC56xP54/60 MCU and external devices.
The DSPI modules provide these features: Full duplex, synchronous transfers Master or slave operation Programmable master bit rates Programmable clock polarity and phase End-of-transmission interrupt flag Programmable transfer baud rate Programmable data frames from 4 to 16 bits Up to 28 chip select lines available 8 each on DSPI_0 and DSPI_1 4 each on DSPI_2, DSPI_3, and DSPI_4 8 clock and transfer attributes registers Chip select strobe available as alternate function on one of the chip select pins for
deglitching FIFOs for buffering up to 5 transfers on the transmit and receive side Queueing operation possible through use of the eDMA General purpose I/O functionality on pins when not used for SPI
1.5.23 eTimer
Two eTimer modules are provided, each with six 16-bit general purpose up/down
timer/counter per module. The following features are implemented: Individual channel capability Input capture trigger Output compare Double buffer (to capture rising edge and falling edge) Separate prescaler for each counter Selectable clock source 0% to 100% pulse measurement Rotation direction flag (Quad decoder mode) Maximum count rate Equals peripheral clock/2 — for external event counting Equals peripheral clock — for internal clock counting Cascadeable counters Programmable count modulo Quadrature decode capabilities Counters can share available input pins Count once or repeatedly Preloadable counters Pins available as GPIO when timer functionality not in use
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1.5.24 Analog-to-digital converter (ADC)
The ADC module provides the following features:
Analog part: 1 on-chip analog-to-digital converter 10-bit AD resolution 1 sample and hold unit per ADC Conversion time, including sampling time, less than 1 μs (at full precision) Typical sampling time is 150 ns min. (at full precision) Differential non-linearity error (DNL) ±1 LSB Integral non-linearity error (INL) ±1.5 LSB Total unadjusted error (TUE) <3 LSB Single-ended input signal range from 0 to 3.3 V / 5.0V ADC and its reference can be supplied with a voltage independent from VDDIO ADC supply can be equal or higher than VDDIO ADC supply and the ADC reference are not independent from each other (they are
internally bonded to the same pad) Sample times of 2 (default), 8, 64, or 128 ADC clock cycles
Digital part: 27 input channels (26 + 1 internally connected) 4 analog watchdogs to compare ADC results against predefined levels (low, high,
range) before results are stored 2 operating modes: Normal mode and CTU control mode Normal mode features Register-based interface with the CPU: control register, status register, 1 result
register per channel ADC state machine managing 3 request flows: regular command, hardware
injected command, and software injected command Selectable priority between software and hardware injected commands DMA compatible interface CTU control mode features Triggered mode only 4 independent result queues (2× 16 entries, 2× 4 entries) Result alignment circuitry (left justified; right justified) 32-bit read mode allows to have channel ID on one of the 16-bit part DMA compatible interfaces
1.5.25 Cross triggering unit (CTU)
The Cross Triggering Unit (CTU) allows automatic generation of ADC conversion requests
on user selected conditions with minimized CPU load for dynamic configuration.
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It implements the following features: Double buffered trigger generation unit with up to eight independent triggers generated
from external triggers Trigger generation unit configurable in sequential mode or in triggered mode Each Trigger can be appropriately delayed to compensate the delay of external low
pass filter Double buffered global trigger unit allowing eTimer synchronization and/or ADC
command generation Double buffered ADC command list pointers to minimize ADC-trigger unit update Double buffered ADC conversion command list with up to 24 ADC commands Each trigger has the capability to generate consecutive commands ADC conversion command allows to control ADC channel from each ADC, single or
synchronous sampling, independent result queue selection
1.5.26 Cyclic redundancy check (CRC) 3 contexts for the concurrent CRC computation Separate CRC engine for each context Zero-wait states during the CRC computation (pipeline scheme) 3 hard-wired polynomials (CRC-8 VDA CAN, CRC-32 ethernet and CRC-16-CCITT) Support for byte/half-word/word width of the input data stream Support for expected and actual CRC comparison
1.5.27 Nexus development interface (NDI)
The NDI block provides real-time development support capabilities for the SPC56xP54/60
Power Architecture based MCU in compliance with the IEEE-ISTO 5001-2003 standard.
This development support is supplied for MCUs without requiring external address and data
pins for internal visibility. The NDI block is an integration of several individual Nexus blocks
that are selected to provide the development support interface for this device. The NDI block
interfaces to the host processor and internal buses to provide development support as per
the IEEE-ISTO 5001-2003 Class 2+ standard. The development support provided includes
access to the MCU’s internal memory map and access to the processor’s internal registers
during run time.
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The Nexus Interface provides the following features: Configured via the IEEE 1149.1 All Nexus port pins operate at VDDIO (no dedicated power supply) Nexus 2+ features supported Static debug Watchpoint messaging Ownership trace messaging Program trace messaging Real time read/write of any internally memory mapped resources through JTAG
pins Overrun control, which selects whether to stall before Nexus overruns or keep
executing and allow overwrite of information Watchpoint triggering, watchpoint triggers program tracing DDR Auxiliary Output Port 4 MDO (Message Data Out) pins MCKO (Message Clock Out) pin 2 MSEO (Message Start/End Out) pins
–EVTO (Event Out) pin Auxiliary Input Port
–EVTI (Event In) pin
1.5.28 IEEE 1149.1 (JTAG) controller
The JTAG controller (JTAGC) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. All data
input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE standard.
The JTAG controller provides the following features: IEEE Test Access Port (TAP) interface with four pins (TDI, TMS, TCK, TDO) Selectable modes of operation include JTAGC/debug or normal system operation. A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions: BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD A 5-bit instruction register that supports the additional following public instructions: ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_CORE0,
ACCESS_AUX_TAP_CORE1, ACCESS_AUX_TAP_NASPS_0,
ACCESS_AUX_TAP_NASPS_1 Three test data registers: a bypass register, a boundary scan register, and a device
identification register. A TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry.
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1.5.29 On-chip voltage regulator (VREG)
The on-chip voltage regulator module provides the following features: Uses external NPN transistor Regulates external 3.3 V to 5.0 V down to 1.2 V for the core logic Low voltage detection on the internal 1.2 V and I/O voltage 3.3V
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2.1 Package pinouts
The LQFP pinouts are shown in the following figures.
Figure 2. LQFP176 pinout (top view)(a) Software development package only. Not available for production.
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Figure 3. LQFP144 pinout (top view)(b) Availability of port pin alternate functions depends on product selection
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Figure 4. LQFP100 pinout (top view)(c)
2.2 Pin descriptions
The following sections provide signal descriptions and related information about the
functionality and configuration of the SPC56xP54/60 devices.
2.2.1 Power supply and reference voltage pins
Table 5 lists the power supply and reference voltage for the SPC56xP54/60 devices.
Availability of port pin alternate functions depends on product selection
Table 5. Supply pins
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Table 5. Supply pins (continued)
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2.2.2 System pins
Table 6 and Table 7 contain information on pin functions for the SPC56xP54/60 devices.
The pins listed in Table 6 are single-function pins. The pins shown in Table 7 are multi-
function pins, programmable via their respective Pad Configuration Register (PCR) values.
LQFP176 available only as development package. See datasheet Voltage Regulator Electrical Characteristics section for more details.
Table 5. Supply pins (continued)
Table 6. System pins
Package pinouts and signal descriptions SPC56xP54x, SPC56xP60x
32/105 Doc ID 18340 Rev 5 SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register. LQFP176 available only as development package. In this pin there is an internal pull, refer to JTAGC chapter in the device reference manual for pull direction. Its configuration can be set up by the PCR[108] register inside the SIU module. See SIUL chapter in the device reference
manual.
Table 6. System pins (continued)
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2.2.3 Pin muxing
Table 7 defines the pin list and muxing for the SPC56xP54/60 devices relative to Full-
featured version.
Each row of Table 7 shows all the possible ways of configuring each pin, via “alternate
functions”. The default function assigned to each pin after reset is the ALT0 function.
Pins marked as external interrupt capable can also be used to resume from STOP and
HALT mode.
SPC56xP54/60 devices provide four main I/O pad types depending on the associated
functions: Slow pads are the most common, providing a compromise between transition time and
low electromagnetic emission. Medium pads provide fast enough transition for serial communication channels with
controlled current to reduce electromagnetic emission. Fast pads provide maximum speed. They are used for improved NEXUS debugging
capability. Symmetric pads are designed to meet FlexRay requirements.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance.
Table 7. Pin muxing(1)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Table 7. Pin muxing(1) (continued)
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Doc ID 18340 Rev 5 47/105 This table concerns Full-featured version. Please refer to “SPC56xP54/60 device configuration difference” table for
difference between Full-featured, and Airbag configuration. ALT0 is the primary (default) function for each port after reset. Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIU module.
PCR[PA]=00→ ALT0; PCR[PA]=01→ ALT1; PCR[PA]=10→ ALT2; PCR[PA]=11→ ALT3. This is intended to select
the output functions; to use one of the input-only functions, the PCR[IBE] bit must be written to ‘1’, regardless of the values
selected in the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is reported as “—”. Module included on the MCU. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMI[PADSELx] bitfields inside the SIUL module. Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register. LQFP176 available only as development package. Weak pull down during reset.
Table 7. Pin muxing(1) (continued)
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3 Electrical characteristics
3.1 Introduction
This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid application of any voltage
higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS). This can be done by the internal pull-up or pull-down, which is provided by the
product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
Caution: All of the following parameter values can vary depending on the application and must be
confirmed during silicon validation, silicon characterization or silicon reliability trial.
3.2 Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 8 are used and
the parameters are tagged accordingly in the tables where appropriate.
Note: The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
Table 8. Parameter classifications
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3.3 Absolute maximum ratings
Table 9. Absolute maximum ratings(1)
Electrical characteristics SPC56xP54x, SPC56xP60x Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device. Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress
have not yet been determined. The difference between each couple of voltage supplies must be less than 300 mV, |VDD_HV_IOy – VDD_HV_IOx | < 300 mV. Guaranteed by device validation Minimum value of TVDD must be guaranteed until VDD_HV_REG reaches 2.6 V (maximum value of VPORH)
Table 9. Absolute maximum ratings(1) (continued)
SPC56xP54x, SPC56xP60x Electrical characteristics
3.4 Recommended operating conditions
Table 10. Recommended operating conditions (5.0V)
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Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.
In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_IOy – VDD_HV_IOx | < 100 mV. To be connected to emitter of external NPN. Low voltage supplies are not under user control—these are produced by an
on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to
high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter. The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash memory module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Table 10. Recommended operating conditions (5.0 V) (continued)
Table 11. Recommended operating conditions (3.3V)
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Figure 7 shows the constraints of the different power supplies. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.
In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_IOy – VDD_HV_IOx | < 100 mV. To be connected to emitter of external NPN. Low voltage supplies are not under user control—these are produced by an
on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to
high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter. The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash memory module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Table 11. Recommended operating conditions (3.3 V) (continued)
