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SNJ55LVDS32WTIN/a5avaiQuad LVDS Receiver


SNJ55LVDS32W ,Quad LVDS Receiverelectrical characteristics• Operate With a Single 3.3-V Supplyof low-voltage differential signaling ..
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SNJ55LVDS32W
Quad LVDS Receiver
300 kΩ300 kΩ
VCC 7 V B Input
50 Ω
VCC
Input
VCC
5 Ω
7 V
Y Output
EQUIVALENT OF EACH A OR B INPUT EQUIVALENT OF G, G, 1,2EN OR
3,4EN INPUTS
TYPICAL OF ALL OUTPUTS

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SN55LVDS32, SN65LVDS32,

SLLS262R
SNx5LVDS3xxxx High-Speed Differential Line Receivers Features 3 Description

The SN55LVDS32, SN65LVDS32, SN65LVDS3486, Meetor Exceed the Requirementsof ANSI and SN65LVDS9637 devices are differentialTIA/EIA-644 Standard receivers that implement the electrical characteristics• Operate Witha Single 3.3-V Supply of low-voltage differential signaling (LVDS). Designedfor Signaling Ratesofupto 150 Mbps signaling technique lowers the output voltage 5-V differential standard levels (such as(See)
422B)to reduce the power, increase the switching• Differential Input Thresholds ±100 mV Max speeds, and allow operation witha 3.3-V supply• Typical Propagation Delay Timeof 2.1ns Any of the differential receivers provides Power Dissipation60 mW Typical Per Receiverat logical output state witha ±100-mV differential
Maximum Data Rate voltage within the input common-mode voltage
The input common-mode voltage range allows• Bus-Terminal ESD Protection Exceeds8 kV ground potential difference between two• Low-Voltage TTL (LVTTL) Logic Output Levels nodes. Pin Compatible With AM26LS32, MC3486, and
μA9637• Open-Circuit Fail-Safe• Cold Sparingfor Space and High-ReliabilityApplications Requiring Redundancy2 Applications• Wireless Infrastructure• Telecom Infrastructure• Printer
(1) Forall available packages, see the orderable addendum
the endofthe data sheet.
Equivalent Input and Output Schematic Diagrams
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