SNJ54LVC138AFK ,3-Line To 8-Line Decoder/DemultiplexerElectrical Characteristics....... 712.1 Related Links.. 146.6 Switching Characteristics—SN54LVC138A ..
SNJ54LVC14AFK ,HEX SCHMITT-TRIGGER INVERTERSFeatures 3 DescriptionThe SN54LVC14A hex Schmitt-trigger inverter is1• Operate From 1.65 V to 3.6 V ..
SNJ54LVC646AW ,OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTSFEATURES• Operate From 1.65 V to 3.6 V • I Supports Partial-Power-Down ModeoffOperation• Inputs Acc ..
SNJ54LVCH244AFK ,Octal Buffer/Driver With 3-State OutputsFEATURES• Operate From 1.65 V to 3.6 V • I Supports Partial-Power-Down ModeoffOperation• Inputs Acc ..
SNJ54LVTH162244WD ,3.3.-V ABT 16-Bit Buffers/Drivers With 3-State OutputsFEATURESSN54LVTH162244 . . . WD PACKAGE• Members of the Texas Instruments Widebus™SN74LVTH162244 . ..
SNJ54LVTH162245WD ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsFEATURESSN54LVTH162245 . . . WD PACKAGE• Members of the Texas Instruments Widebus™SN74LVTH162245 . ..
SR086SG-G , Adjustable Off-Line Inductorless Switching Regulator
SR10100 , SCHOTTKY BARRIER RECTIFIER Reverse Voltage - 20 to 200 Volts Forward Current - 10.0Amperes
SR10150S , 10.0AMP Schottky Barrier Rectifiers
SR10200 , SCHOTTKY BARRIER RECTIFIER Reverse Voltage - 20 to 200 Volts Forward Current - 10.0Amperes
SR1050 , SCHOTTKY BARRIER RECTIFIER Reverse Voltage - 20 to 200 Volts Forward Current - 10.0Amperes
SR106 ,YI ELECTRONIC CO., LTD. - MINIATURE SCHOTTKY BARRIER RECTIFIER
SN54LVC138A-SNJ54LVC138AFK
3-Line To 8-Line Decoder/Demultiplexer
Sample & Support & Product Tools & Technical Community Buy Folder Documents Software SN54LVC138A, SN74LVC138A SCAS291W – MARCH 1993 – REVISED OCTOBER 2016 SN74LVC138A 3-Line to 8-Line Decoders Demultiplexers 1 Features 3 Description The SN74LVC138A devices are designed for high- 1• Operate From 1.65 V to 3.6 V performance memory-decoding or data-routing • Inputs Accept Voltages to 5.5 V applications requiring very short propagation delay • Max t of 5.8 ns at 3.3 V pd times. In high-performance memory systems, these decoders minimize the effects of system decoding. • Typical V (Output Ground Bounce) OLP When employed with high-speed memories using a < 0.8 V at V = 3.3 V, T = 25°C CC A fast enable circuit, delay times of these decoders and • Typical V (Output V Undershoot) OHV OH the enable time of the memory usually are less than > 2 V at V = 3.3 V, T = 25°C CC A the typical access time of the memory. This means • Latch-Up Performance Exceeds 250 mA Per that the effective system delay introduced by the JESD 17 decoders is negligible. (1) Device Information 2 Applications PART NUMBER PACKAGE BODY SIZE (NOM) • LED Displays LCCC (20) 8.89 mm × 8.89 mm • Servers CDIP (16) 19.56 mm × 6.92 mm • White Goods CFP (16) 10.30 mm × 6.73 mm • Power Infrastructure SOIC (16) 9.90 mm × 3.91 mm • Building Automation SSOP (16) 6.20 mm × 5.30 mm SNx4LVC138A • Factory Automation TVSOP (16) 3.60 mm × 4.40 mm BGA MICROSTAR 4.00 mm × 3.00 mm JUNIOR (20) TSSOP (16) 5.00 mm × 4.40 mm UQFN (16) 2.60 mm × 1.80 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) 15 Y0 1 A 14 Y1 Select 2 B 13 Inputs Y2 3 12 Y3 C Data Outputs 11 Y4 10 Y5 6 9 G1 Y6 4 Enable 7 G2A Inputs Y7 5 G2B Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages. Copyright © 2016, 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
