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SNJ54AHCT125JTIN/a40avaiQuadruple Bus Buffer Gates With 3- State Outputs


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SNJ54AHCT125J
Quadruple Bus Buffer Gates With 3- State Outputs
SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O − DECEMBER 1995 − REVISED JULY 2003 Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)

1OE
2OE
GND
VCC
4OE
3OE
SN54AHCT125 ...J OR W PACKAGE
SN74AHCT125 ...D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
12019
91011 1213
3OE
2OE1OENC3A4OE
GND
SN54AHCT125... FK PACKAGE
(TOP VIEW)

NC − No internal connection
SN74AHCT125... RGY PACKAGE
(TOP VIEW)

4OE
3OE
2OE
1OE
GND
description/ordering information

The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective
gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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