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SN74SSQE32882ZALRTIN/a1739avaiJEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
SN74SSQE32882ZCJRTIN/a89avai JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test


SN74SSQE32882ZALR ,JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85FEATURESoperation associated with the Quad Chip Select2• JEDEC SSTE32882 CompliantEnable (QCSEN) in ..
SN74SSQE32882ZCJR , JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Testmaximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
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SN74SSQE32882ZALR-SN74SSQE32882ZCJR
JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
1FEATURES
APPLICATIONS
DESCRIPTION/ORDERING INFORMATION
SN74SSQE32882
www.ti.com.................................................................................................................................................
SCAS857A–MARCH 2008–REVISED OCTOBER 2008
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST
ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER

The SN74SSQE32882 has two basic modes of
operation associated with the Quad Chip Select JEDEC SSTE32882 Compliant Enable (QCSEN) input.• 1-to-2 Register Outputs and 1-to-4 Clock Pair
First, when the QCSEN input pinis openor pulledOutputs Support Stacked DDR3 DIMMs high, the component has two chip select inputs,• Chip Select Inputs Prevent Data Outputs from DCS0 and DCS1, and two copiesof each chip selectChanging State and Minimize System Power output, QACS0, QACS1, QBCS0 and QBCS1. ThisConsumption modeis the QuadCS disabled mode. Alternatively,
when the QCSEN input pin is pulled low, the• 1.5-V Phase Lock Loop Clock Driver Buffers
component has four chip select inputs DCS[3:0], andOne Differential Clock Pair (CK and CK) and
four chip select outputs, QCS[3:0]. This modeis theDistributesto Four Differential Outputs QuadCS enabled mode.• 1.5-V CMOS Inputs
When QCSENis high or floating, the device also• Checks Parity on Command and Address supports an operating mode that allowsa single(CS-gated) Data Inputs deviceto be mounted on the back sideofa DIMM• Supports LVCMOS Switching Levels on array. This device can then be configuredto keep theRESET Input input bus termination (IBT) feature enabled for all
input signals independent of MIRROR. The• RESET Input:
SN74SSQE32882. operates froma differential clock– Disables Differential Input Receivers (CK and CK). Data are registeredat the crossingof– Resets All Registers CK going high and CK going low. This data can either re-drivento the outputsor usedto access internal– Forces All Outputs into Pre-defined States
control registers. Details are coveredin the Function• Optimal Pinout for DDR3 DIMM PCB Layout Tables (each flip-flop) with QCSEN= low.• Supports Four Chip Selects
Input bus data integrityis protected bya parity• Single Register Backside Mount Support function. All address and command input signals are
summed; the lastbitof the sumis then comparedto
the parity signal delivered by the system at the• DDR3 Registered DIMMs upto DDR3-1333 PAR_IN input one clock cycle later.If these two
values do not match, the device pulls the open drain• Single-, Dual- and Quad-Rank RDIMM
output ERROUT low. The control signals (DCKE0,
DCKE1, DODT0, DODT1, and DCS[n:0]) are not part this computation.This JEDEC SSTE32882-compliant, 28-bit 1:2 or The SN74SSQE32882 implements different26-bit 1:2 and 4-bit 1:1 registering clock driver with power-saving mechanismsto reduce thermal powerparityis designed for operation on DDR3 Registered dissipation andto support system power-down states.DIMMsupto DDR3-1333 with VDDof 1.5V. Power consumptionis further reduced by disablingAll inputs are 1.5-V, CMOS-compatible. All outputs unused outputs.are 1.5-V CMOS drivers optimizedto drive DRAM The package design is optimal for high-densitysignals on terminated traces in DDR3 RDIMM DIMMs. By aligning input and output positionsapplications. Clock outputs Yn and Yn and control net towards DIMM finger-signal ordering and SDRAMoutputs DxCKEn, DxCSn, and DxODTn can each be ballout, the device de-scrambles the DIMM tracesdriven witha different strength and skewto optimize and allows low crosstalk designs with lowsignal integrity, compensate for different loading, and interconnect latency. Edge-controlled outputs reducebalance signal travel speed. ringing and improve signal eye opening at the
SDRAM inputs.
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