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SN74LVTH16952TIN/a20avai3.3 V ABT 16-Bit Registered Transceivers With 3-State Outputs
SN74LVTH16952DGGRTIN/a1000avai3.3 V ABT 16-Bit Registered Transceivers With 3-State Outputs
SN74LVTH16952DLTIN/a79avai3.3 V ABT 16-Bit Registered Transceivers With 3-State Outputs


SN74LVTH16952DGGR ,3.3 V ABT 16-Bit Registered Transceivers With 3-State Outputs SN54LVTH16952, SN74LVTH16952 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS697G ..
SN74LVTH16952DL ,3.3 V ABT 16-Bit Registered Transceivers With 3-State Outputs SN54LVTH16952, SN74LVTH16952 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS697G ..
SN74LVTH182512 ,3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICESWITH 18-BI ..
SN74LVTH182512DGGR ,3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICESWITH 18-BI ..
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SN74LVTH16952-SN74LVTH16952DGGR-SN74LVTH16952DL
3.3 V ABT 16-Bit Registered Transceivers With 3-State Outputs
Dissipation Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description

The ’LVTH16952 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) VCC operation, but
with the capability to provide a TTL interface to a 5-V system environment.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored
in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable
(CLKENAB or CLKENBA) input is low. T aking the output-enable (OEAB or OEBA) input low accesses the data
on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1CLKENAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6CC
2A7
2A8
GND
2CLKENAB
2CLKAB
2OEAB
1CLKENBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6CC
2B7
2B8
GND
2CLKENBA
2CLKBA
2OEBA
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