SN74LVTH16835DGGR ,3.3-V ABT 18-Bit Universal Bus Drivers With 3-State Outputs SN54LVTH16835, SN74LVTH16835 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERSWITH 3-STATE OUTPUTSSCBS713C – ..
SN74LVTH16952 ,3.3 V ABT 16-Bit Registered Transceivers With 3-State Outputs SN54LVTH16952, SN74LVTH16952 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS697G ..
SN74LVTH16952DGGR ,3.3 V ABT 16-Bit Registered Transceivers With 3-State Outputs SN54LVTH16952, SN74LVTH16952 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS697G ..
SN74LVTH16952DL ,3.3 V ABT 16-Bit Registered Transceivers With 3-State Outputs SN54LVTH16952, SN74LVTH16952 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS697G ..
SN74LVTH182512 ,3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICESWITH 18-BI ..
SN74LVTH182512DGGR ,3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICESWITH 18-BI ..
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SN74LVTH16835DGGR
3.3-V ABT 18-Bit Universal Bus Drivers With 3-State Outputs
Dissipation Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC) Support Unregulated Battery Operation
Down to 2.7 V Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot
Insertion Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB
Layout Latch-Up Performance Exceeds 500 mA Per
JESD 17 ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
descriptionThe ’LVTH16835 devices are 18-bit universal bus drivers designed for low-voltage (3.3-V) VCC operation, but
with the capability to provide a TTL interface to a 5-V system environment.
Data flow from A to Y is controlled by the output-enable (OE) input. These devices operate in the transparent
mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high
or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of the clock.
When OE is high, the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
GND
VCC
GND
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
GND
VCC
GND
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
