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Home ›  SS77 > 74LVTH16374DLRG4-SN74LVTH16374-SN74LVTH16374DGGR-SN74LVTH16374DL-SN74LVTH16374DLG4-SN74LVTH16374DLR-SN74LVTH16374GRDR,3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs
74LVTH16374DLRG4-SN74LVTH16374-SN74LVTH16374DGGR-SN74LVTH16374DL-SN74LVTH16374DLG4 Fast Delivery,Good Price
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SN74LVTH16374TIN/a180avai3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs
SN74LVTH16374DGGRTI ?N/a8034avai3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs
SN74LVTH16374DLTIN/a839avai3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs
SN74LVTH16374DLG4TIN/a19avai3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 48-SSOP -40 to 85
SN74LVTH16374DLRTI ?N/a720avai3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs
SN74LVTH16374GRDRTIN/a3985avai3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 54-BGA MICROSTAR JUNIOR -40 to 85
74LVTH16374DLRG4TIN/a94avai3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 48-SSOP -40 to 85


SN74LVTH16374DGGR ,3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State OutputsSCBS145R–MAY 1992–REVISED AUGUST 2007DESCRIPTION/ORDERING INFORMATION (CONTINUED)When V is between ..
SN74LVTH16374DL ,3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State OutputsLOGIC DIAGRAM (POSITIVE LOGIC)1 241OE 2OE48 252CLK1CLKC1 C12 132Q11Q147 361D1D1 1D 2D1To Seven Othe ..
SN74LVTH16374DLG4 ,3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 48-SSOP -40 to 85/packaging.(2) For the most current package and ordering information, see the Package Option Addend ..
SN74LVTH16374DLR ,3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State OutputsSCBS145R–MAY 1992–REVISED AUGUST 2007(1)GQL OR ZQL PACKAGETERMINAL ASSIGNMENTS(TOP VIEW)(56-Ball GQ ..
SN74LVTH16374GRDR ,3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 54-BGA MICROSTAR JUNIOR -40 to 85SCBS145R–MAY 1992–REVISED AUGUST 20071
SN74LVTH16374ZRDR , 3.3V ABT 16 BIT EDGE - TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SP720ABT , TVS Diode Arrays - Elctronic Protection Array for ESD and Overvoltage Protection
SP720AB-T , TVS Diode Arrays - Elctronic Protection Array for ESD and Overvoltage Protection
SP721 , ELECTRONIC PROTECTION ARRAY FOR ESD AND OVER-VOLTAGE PROTECTION
SP721ABT , ELECTRONIC PROTECTION ARRAY FOR ESD AND OVER-VOLTAGE PROTECTION
SP723AB , TVS Diode Arrays - Electronic Protection Array for ESD and Overvoltage Protection
SP723AB , TVS Diode Arrays - Electronic Protection Array for ESD and Overvoltage Protection


74LVTH16374DLRG4-SN74LVTH16374-SN74LVTH16374DGGR-SN74LVTH16374DL-SN74LVTH16374DLG4-SN74LVTH16374DLR-SN74LVTH16374GRDR
3.3-V ABT 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs 48-SSOP -40 to 85
SN54LVTH16374.SN74LVTH16374... DGG OR DL PACKAGE
(TOP VIEW)

1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
DESCRIPTION/ORDERING INFORMATION
SN54LVTH16374,, SN74LVTH16374 ABT 16-BIT EDGE-TRIGGERED FLIP-FLOPS Membersof the Texas Instruments Widebus™
Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
Support Mixed-Mode Signal Operation
Input and Output Voltages With 3.3-V
Support Unregulated Battery Operation 2.7V Typical VOLP (Output Ground Bounce)Vat
VCC= 3.3V, TA= 25°C
Ioff and Power-Up 3-State Support Hot Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD17
ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
The 'LVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs for low-voltage
(3.3-V) VCC operation, but with the capabilityto providea TTL interfacetoa 5-V system environment. These
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional drivers, and working
registers.
These devices can be usedas two 8-bit flip-flopsor one 16-bit flip-flop. On the positive transitionof the clock
(CLK), theQ outputsof the flip-flop takeon logic levels setupat the data (D) inputs. buffered output-enable (OE) input canbeto place the eight outputsin eithera logic state (highor
low logic levels)ora high-impedance state. the high-impedance state, the outputs load nor drive the
bus lines significantly. The high-impedance and the increased drive provide theto drive bus lines
without need for interfaceor pullup components. does not affect internal operationsof the Old data canbe retainedor new canbe entered while
the outputs arein the high-impedance state.
Active bus-hold circuitry holds unusedor undriven inputsata valid logic state. Useof pullupor pulldown resistors
with the bus-hold circuitryis not recommended.
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