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SN74LVTH16373DGGR ,3.3-V ABT 16-Bit Transparent D-Type Latches With 3-State OutputsSN54LVTH16373,, SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS
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SN74LVTH16373DLG4 ,3.3-V ABT 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85FEATURESSN54LVTH16373 . . . WD PACKAGE• Members of the Texas Instruments Widebus™SN74LVTH16373 . . ..
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74LVTH16245ADGGRG4-74LVTH16245ADGVRG4-74LVTH16245ADLG4-SN74LVTH16245A-SN74LVTH16245ADGGR-SN74LVTH16245ADGVR-SN74LVTH16245ADL-SN74LVTH16245ADLR
3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN54LVTH16245A... WD PACKAGESN74LVTH16245A... DGG, DGV, OR DL PACKAGE
(TOP VIEW)1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
DESCRIPTION/ORDERING INFORMATION
SN54LVTH16245A,,
SN74LVTH16245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS Membersof the Texas Instruments Widebus™
Family State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down 2.7V Typical VOLP (Output Ground Bounce) <0.8V VCC= 3.3V,TA= 25°C Distributed VCC and GND Pins Minimize
High-Speed Switching Noise Flow-Through Architecture Optimizes PCB
Layout Ioff and Power-Up 3-State Support Hot
Insertion Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 500 mA Per
JESD17 ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)The 'LVTH16245A devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for
(3.3-V) VCC operation, but with the capabilityto provide interfacetoa 5-V system environment.
The devices are designed for asynchronous communication between two data buses. The logicof the
direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs the A-port
outputsor place both output ports into the high-impedance mode. The device transmits data fromA busto
theB bus when the B-port outputs are activated, and theB busto theA bus when the A-port are
activated. The input circuitryon bothA andB portsis active and must havea logic HIGH LOW level
appliedto prevent excess ICC and ICCZ.
Active bus-hold circuitry holds unusedor undriven inputsata valid logic state. Useof pullup pulldown
resistors with the bus-hold circuitryis not recommended.
When VCCis between0 and 1.5V, the devices arein the state during powerupor down.to ensure the high-impedance state above 1.5 OE should be tiedto VCC througha pullup resistor; valueof the resistoris determinedby the capabilityof the driver. devices for hot-insertion applications usingIoff and power-up 3-state. The Ioff circuitry the outputs, preventing through the devices when they are powered down. 3-state circuitry state during powerup and down,
which prevents driver conflict.
