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SP707CP , Low Power Microprocessor Supervisory Circuits
SP707CP , Low Power Microprocessor Supervisory Circuits
SP707CP , Low Power Microprocessor Supervisory Circuits
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SN74LVT8986PM
3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) Tap Transceiver
www.ti.com
FEATURES
DESCRIPTION/ORDERING INFORMATION
SN54LVT8986,, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759E–OCTOBER 2002–REVISED MAY 2007 Membersof the Texas Instruments (TI) Family •
Bypass (BYP5 –BYP0) Forces Primaryto JTAG Scan-Support Products Configured Secondary Paths Without Useof
Linking Shadow Protocols•
Extend Scan Access From Board Levelto
Higher Levelof System Integration •
Connect (CON2 –CON0) Provides Indicationof
Primary-to-Secondary Paths Connections•
Three IEEE Std 1149.1-Compatible
Configurable High
Primary Scanof the•
Multiple DevicesSecondary Scan
PathIOL)
Support Backplane Interfaceat Primary•
Simple (Linking Shadow) ProtocolIs Usedto
Outputs and High Fanoutat SecondaryConnect the Primary Test Access Port (TAP)
Outputsto Secondary TAPs. This Single ProtocolIs
Usedto Address and Configure the •
While Poweredat 3.3V, Both Primary and
Secondary Scan Path. Secondary TAPs Are Fully5V Tolerant for
Interfacing5V and/or 3.3V Masters and•
LASP (8986) and ASP (8996) Can Be TargetsConfigured on the Same Backplane Using
Similar Shadow Protocols •
Package Options Include Plastic BGA (GGV)
and LQFP (PM) Packages and Ceramic Quad•
Linking Shadow Protocols Can Occurin Any
Flat (HV) Packages Using 25-milof Test Logic Reset, Run Test/Idle, Pause DR,
Center-to-Center SpacingPauseIR TAP Statesto Provide
Board-to-Board and BuiltIn Self TestThe 'LVT8986 linking addressable scan ports (LASPs) are membersof theTI familyof IEEE Std 1149.1 (JTAG)
scan-support products. The scan-support product family facilitates testingof fully boundary-scannable devices.
The LASP applies linking shadow protocols through the test access port (TAP)to extend scan accessto the
system level and divide scan chainsat the board level.
The LASP consistsofa primary TAP for interfacingto the backplane IEEE Std 1149.1 serial-bus signals (PTDI,
PTMS, PTCK, PTDO, PRTST) and three secondary TAPs for interfacingto the board-level IEEE Std 1149.1
serial-bus signals. Each secondary TAP consistsof signals STDIx, STMSx, STCKx, STDOx, and STRSTx.
Conceptually, the LASPisa gateway device that canbe usedto connecta setof primary TAP signalstoa setof
secondary TAP signals– for example,to interface backplane TAP signalstoa board-level TAP. The LASP
provides all signal buffering that might be required at these two interfaces. Primary-to-secondary TAP
connections can be configured with the helpof linking shadow protocolor protocol bypass (BYP5–BYP0) inputs.
All possible configurations are tabulatedin Function Tables1,2, and3.
ORDERING INFORMATION PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKINGPBGA– GGV SN74LVT8986GGV LVT8986
–40°Cto 85°C PBGA– ZGV SN74LVT8986ZGV LVT8986
LQFP– PM SN74LVT8986PM LVT8986
–55°Cto 125°C CFP–HV SNJ54LVT8986HV SNJ54LVT8986HV Package standard data, symbolization, and PCB design
guidelines available
