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SN74LVCH32373AGKERTIN/a32avai32-Bit Transparent D-Type Latch With 3-State Outputs
SN74LVCH32373AGKERN/a45avai32-Bit Transparent D-Type Latch With 3-State Outputs
SN74LVCH32373AZKERTIN/a9avai32-Bit Transparent D-Type Latch With 3-State Outputs


SN74LVCH32373AGKER ,32-Bit Transparent D-Type Latch With 3-State OutputsFEATURES • Supports Mixed-Mode Signal Operation(5-V Input and Output Voltages With• Member of the T ..
SN74LVCH32373AGKER ,32-Bit Transparent D-Type Latch With 3-State OutputsSCAS618D–OCTOBER 1998–REVISED MARCH 2005GKE PACKAGETERMINAL ASSIGNMENTS(TOP VIEW)1 2 3 4 5 61 2 3 4 ..
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SN74LVCH32373AGKER-SN74LVCH32373AZKER
32-Bit Transparent D-Type Latch With 3-State Outputs
www.ti.com
FEATURES
DESCRIPTION/ORDERING INFORMATION
SN74LVCH32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS

SCAS618D–OCTOBER 1998–REVISED MARCH 2005 Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
Memberof the Texas Instruments Widebus+™
3.3-V VCC)Family
Bus Hold on Data Inputs Eliminates the Need Operates From 1.65Vto 3.6V
for External Pullup/Pulldown Resistors
Inputs Accept Voltagesto 5.5V Latch-Up Performance Exceeds 250 mA Per Maxtpdof 4.2 nsat 3.3V JESD17 Typical VOLP (Output Ground Bounce) ESD Protection Exceeds JESD22<0.8Vat VCC= 3.3V,TA= 25°C – 2000-V Human-Body Model (A114-A) Typical VOHV (Output VOH Undershoot) 200-V Machine Model (A115-A)>2Vat VCC= 3.3V, TA= 25°C I Supports Partial-Power-Down Mode
This 32-bit transparent D-type latchis designed for 1.65-Vto 3.6-VVCC operation.
The SN74LVCH32373Ais particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.It canbe usedas four 8-bit latches, two 16-bit latches,or one 32-bit latch. When
the latch-enable (LE) inputis high, theQ outputs follow the data (D) inputs. When LEis taken low, theQ outputs
are latchedat the levels setupat theD inputs. buffered output-enable (OE) input canbe usedto place the eight outputsin eithera normal logic state (highor
low logic levels)or the high-impedance state.In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capabilityto drive bus lines
without interfaceor pullup components. does not affect internal operationsof the latch. Old data can be retainedor new data can be entered while
the outputs arein the high-impedance state.
Inputs canbe driven from either 3.3-Vor 5-V devices. This feature allows the useof these devicesas translatorsa mixed 3.3-V/5-V system environment.
This deviceis fully specified for partial-power-down applications usingIoff. TheIoff circuitry disables the outputs,
preventing damaging current through the device whenitis powered down. ensure the high-impedance state during power upor power down, OE should be tiedtoVCC througha pullup
resistor; the minimum valueof the resistoris determinedby the current-sinking capabilityof the driver.
Active bus-hold circuitry holds unusedor undriven inputsata valid logic state. Useof pullupor pulldown resistors
with the bus-hold circuitryis not recommended.
ORDERING INFORMATION PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING

–40°Cto 85°C LFBGA– GKE Tape and reel SN74LVCH32373AGKER CH373A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelinesare availableat
www.ti.com/sc/package.
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