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74LVC1G373DCKRE4-SN74LVC1G373DBVR-SN74LVC1G373DCKR Fast Delivery,Good Price
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74LVC1G373DCKRE4TIN/a6avaiSingle D-Type Latch with 3S Output 6-SC70 -40 to 125
SN74LVC1G373DBVRTIN/a915avaiSingle D-Type Latch with 3S Output
SN74LVC1G373DCKRTIN/a719avaiSingle D-Type Latch with 3S Output


SN74LVC1G373DBVR ,Single D-Type Latch with 3S OutputElectrical Characteristics....... 612 Device and Documentation Support........ 176.6 Timing Require ..
SN74LVC1G373DCKR ,Single D-Type Latch with 3S OutputFeatures 3 DescriptionThe SN74LVC1G373 device is a single D-type latch1• Available in the Texas Ins ..
SN74LVC1G374DBVR ,Single D-Type Flip-Flop with 3-State OutputFEATURESa major breakthrough in IC packaging concepts,2• Available in the Texas Instruments NanoSta ..
SN74LVC1G374DCKR ,Single D-Type Flip-Flop with 3-State Output SCES520C–DECEMBER 2003–REVISED DECEMBER 2013(1)Recommended Operating ConditionsMIN MAX UNITOperati ..
SN74LVC1G386DBVR ,SINGLE 3-INPUT POSITIVE-XOR GATE SCES439E–APRIL 2003–REVISED DECEMBER 2013(1)Recommended Operating ConditionsMIN MAX UNITOperating ..
SN74LVC1G386DCKR ,SINGLE 3-INPUT POSITIVE-XOR GATEmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
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74LVC1G373DCKRE4-SN74LVC1G373DBVR-SN74LVC1G373DCKR
Single D-Type Latch with 3S Output 6-SOT-23 -40 to 125
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SN74LVC1G373

SCES528F –DECEMBER 2003–REVISED MAY 2017
SN74LVC1G373 Single D-Type Latch With 3-State Output Features
Availablein the Texas Instruments
NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltagesto 5.5V Provides Down Translationto VCC Maxtpdof4nsat 3.3V Low Power Consumption: 10-μA
Maximum ICC ±24-mA Output Driveat 3.3V Ioff Supports Partial-Power-Down Mode and Back
Drive Protection Latch-Up Performance Exceeds 100 mA
Per JESD 78, ClassII Applications Servers Printers Telecom and Grid Infrastructure Memory Addressing Buffer Registers Electronic Pointof Sale Description
The SN74LVC1G373 deviceisa single D-type latch
designed for 1.65-Vto 5.5-V VCC operation.
This deviceis particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers,
and working registers. While the latch-enable (LE)
inputis high, theQ outputs follow the data (D) inputs.
When LEis taken low, theQ outputs are latchedat
the logic levels setupat theD inputs.
NanoFree™ package technology is a major
breakthroughinIC packaging concepts, using the die the package. does not affect the internal operations of the
latch. Old data can be retainedor new data can be
entered while the outputs arein the high-impedance
state.
Device Information(1)

(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
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