SN74LVC1G332DCKR ,Single 3-Input Positive-OR GateFEATURES DESCRIPTIONThe SN74LVC1G332 device performs the Boolean2• Available in the Texas Instrumen ..
SN74LVC1G332DRLR ,Single 3-Input Positive-OR Gate 6-SOT -40 to 125 SCES489E–SEPTEMBER 2003–REVISED DECEMBER 2013(1)Recommended Operating ConditionsMIN MAX UNITOperat ..
SN74LVC1G332YZPR ,Single 3-Input Positive-OR Gatemaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74LVC1G34DBVR ,Single Buffer GateBlock Diagram... 113 Description....... 19.3 Feature Description.... 114 Simplified Schematic 19.4 ..
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SN74LVC1G332DBVR-SN74LVC1G332DCKR-SN74LVC1G332DRLR-SN74LVC1G332YZPR
Single 3-Input Positive-OR Gate 6-SOT-23 -40 to 125
DBV PACKAGE
(TOP VIEW)GND VCC5 4B Y1A C
DCK PACKAGE
(TOP VIEW) 4BGNDA
VCC C
DRY PACKAGE
(TOP VIEW) VCC 6 Y1
YZP PACKAGE
(BOTTOM VIEW)GND VCC Y C
DSF PACKAGE
(TOP VIEW)VCCA B CorYA•B•C
SN74LVC1G332
www.ti.com SCES489E –SEPTEMBER 2003–REVISED DECEMBER 2013
Single 3-Input Positive-OR Gate
Checkfor Samples: SN74LVC1G332
1FEATURES DESCRIPTIONThe SN74LVC1G332 device performs the Boolean
Availablein the Texas Instruments NanoStar™function in
and NanoFree™ Packages positive logic.
• Supports 5-V VCC OperationNanoStar™ and NanoFree™ package technologyis
• Inputs Accept Voltagesto 5.5V a major breakthrough in IC packaging concepts,
• Supports Down Translationto VCC using the dieas the package.
Max tpdof 4.5 nsat 3.3V This deviceis fully specified for partial-power-down
• Low Power Consumption, 10-µA Max ICC applications using Ioff. The Ioff circuitry disables the
±24-mA Output Driveat 3.3V outputs, preventing damaging current backflow
through the device whenitis powered down.
• Ioff Supports Live Insertion, Partial-Power-
Down Mode, and Back-Drive Protection Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
