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SN74LVC1G00IDCKREP-SN74LVC1G00MDCKREP-V62/04732-02XE
Enhanced Product Single 2-Input Positive-Nand Gate 5-SC70 -40 to 85
www.ti.com
FEATURES
DBV OR DCK PACKAGE
(TOP VIEW)GND
VCC
DESCRIPTION/ORDERING INFORMATION
SN74LVC1G00-EP
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES450D–DECEMBER 2003–REVISED SEPTEMBER 2006 Controlled Baseline •
Ioff Supports Partial-Power-Down Mode
Operation– One Assembly/Test Site, One Fabrication
Site •
Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII•
Enhanced Diminishing Manufacturing
Sources (DMS) Support •
ESD Protection Exceeds JESD22 Enhanced Product-Change Notification Human-Body Model (A114-A) Qualification Pedigree(1)
Model (A115-A) Supports 5-VVCC Operation Charged-Device Model (C101) Inputs Accept Voltagesto 5.5V Maxtpdof 3.8nsat 3.3V Low Power Consumption, 10-μA MaxICC ±24-mA
Output Driveat 3.3V(1) Component qualificationin accordance with JEDEC and
industry standardsto ensure reliable operation overan
performance and environmental limits.
This single 2-input positive-NAND gateis designedfor 1.65-Vto 5.5-V VCC operation.
The SN74LVC1G00 performs the Boolean functionY=orY=+in positive logic.
This deviceis fully specified for partial-power-down applications using Ioff. TheIoff circuitry disables the outputs,
preventing damaging current backflow through the device whenitis powered down.
ORDERING INFORMATION PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING(2)–40°Cto 85°C SOP (SC-70)– DCK Reelof 3000 SN74LVC1G00IDCKREP CAO
SOP– DBV Reelof 3000 SN74LVC1G00MDBVREP SBFM–55°Cto 125°C SOP (SC-70)– DCK Reelof 3000 SN74LVC1G00MDCKREP BYA
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelinesare availableat
www.ti.com/sc/package.
(2) The actual top-side marking has one additional character that designatesthe assembly/test site.
FUNCTION TABLE
INPUTS OUTPUT
