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SN74LVC112A-SN74LVC112ADBR-SN74LVC112ADGVR-SN74LVC112ADGVRG4-SN74LVC112ADR Fast Delivery,Good Price
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SN74LVC112ATIN/a148avaiDual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
SN74LVC112ADBRTI Pb-freeN/a2000avaiDual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
SN74LVC112ADGVRTIN/a79avaiDual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
SN74LVC112ADGVRG4TI/BBN/a14avaiDual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-TVSOP -40 to 125
SN74LVC112ADRTI N/a190avaiDual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
SN74LVC112ANSRTIN/a2avaiDual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
SN74LVC112APWTIN/a175avaiDual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
SN74LVC112APWRTEXASN/a4000avaiDual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
SN74LVC112APWRTIN/a3586avaiDual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset


SN74LVC112APWR ,Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And PresetElectrical Specifications table. ....... 6• Added Timing Requirements table for –40°C to 125°C temp ..
SN74LVC112APWR ,Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And PresetFeatures... 1 8 Parameter Measurement Information 82 Applications..... 1 9 Detailed Description. 99 ..
SN74LVC125AD ,Quadruple Bus Buffer Gate With 3-State OutputsTable of Contents9.1 Overview.... 91
SN74LVC125ADB , QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC125ADBR ,Quadruple Bus Buffer Gate With 3-State OutputsMaximum Ratings . 412 Layout.... 117.2 ESD Ratings........ 412.1 Layout Guidelines.... 117.3 Recomm ..
SN74LVC125ADBRG4 ,Quadruple Bus Buffer Gate With 3-State Outputs 14-SSOP -40 to 125features independent line• Operates From 1.65 V to 3.6 Vdrivers with 3-state outputs. Each output i ..
SP3494EN-L , Compatibility with the MAX3486 and 75176 Industry Standard Pinout
SP3508EF-L , Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver with Programmable DCE/DTE and Termination Resistors
SP385ACT , 3V to 5V RS-232 Line Driver/Receiver
SP385ACT , 3V to 5V RS-232 Line Driver/Receiver
SP385EET , Enhanced 3V or 5V RS-232 Line Driver/Receiver
SP4082EEN-L , 5V RS-485/RS-422 Transceivers 1/8th Unit Load, Slew-Rate Limited, ±15kV ESD-Protected


SN74LVC112A-SN74LVC112ADBR-SN74LVC112ADGVR-SN74LVC112ADGVRG4-SN74LVC112ADR-SN74LVC112ANSR-SN74LVC112APW-SN74LVC112APWR
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
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SN74LVC112A

SCAS289M –JANUARY 1993–REVISED DECEMBER 2014
SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop
With Clear And Preset Features 2 Applications
Operates From 1.65Vto 3.6V • Servers Inputs Accept Voltagesto 5.5V • PCs Maxtpdof 4.8nsat 3.3V • Notebooks Typical VOLP (Output Ground Bounce) • Network switches 0.8Vat VCC= 3.3V,TA= 25°C • Toys Typical VOHV (Output VOH Undershoot) • I/O Expanders2Vat VCC= 3.3V,TA= 25°C • Electronic Pointsof Sale Latch-Up Performance Exceeds 250 mA Per
JESD17 3 Description ESD Protection Exceeds JESD22 This dual negative-edge-triggered J-K flip-flop is
designed for 1.65-Vto 3.6-V VCC operation.– 3000-V Human-Body Model 200-V Machine Model Device Information(1) 1500-V Charged-Device Model
(1) Forall available packages, see the orderable addendumat
the endofthe datasheet. Simplified Schematic
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