SN74LV74AQPWRQ1 ,Dual Positive-Edge-Triggered D-Type Flip-FlopsSN74LV74A-Q1DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPSCLS556B − DECEMBER 2003 − REVISED APRIL 2 ..
SN74LV74ARGYR ,Dual Positive-Edge-Triggered D-Type Flip-Flops SCLS381M–AUGUST 1997–REVISED MARCH 20155 Pin Configuration and FunctionsD, DGV, NS, or PW Package1 ..
SN74LV8151NT , 10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS
SN74LV8151PW ,10-Bit Universal Schmitt-Trigger Buffers With 3-State Outputslogic diagram223PA322B N131T/C OE4D121Y1To Seven Other Channels2POST OFFICE BOX 655303 • DALLAS, TE ..
SN74LV8151PWR ,10-Bit Universal Schmitt-Trigger Buffers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV8151PWRG4 , 10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS
SP3243EUEA-L , 3 Driver/5 Receiver Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3244EEY-L , 3.0V to 5.5V RS-232 Transceivers with Auto On-Line® Plus
SP3481CP , 3.3V Low Power Half-Duplex RS-485 Transceivers with 10Mbps Data Rate
SP3481EP , 3.3V Low Power Half-Duplex RS-485 Transceivers with 10Mbps Data Rate
SP3481EP , 3.3V Low Power Half-Duplex RS-485 Transceivers with 10Mbps Data Rate
SP3483CN , 3.3V Low Power Slew Rate Limited Half-Duplex RS-485 Transceiver
SN74LV74AQPWRQ1
Automotive Catalog Dual Positive-Edge-Triggered D-Type Flip-Flop
<0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on
All Ports Ioff Supports Partial-Power-Down Mode
Operation Latch-Up Performance Exceeds 250 mA Per
JESD 17 ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering informationSThis dual positive-edge-triggered D-type flip-flop is designed for 2-V to 5.5-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION� For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at http://www.ti.com. Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
1CLK
1PRE
GND
2CLK
2PRE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
