SN74LV595AQPWRQ1 ,Automotive Catalog 8-Bit Shift Registers With 3-State Output Registers 16-TSSOP -40 to 125FEATURES• Qualified for Automotive Applications Q VB 1 16 CCQ Q2 15• Customer-Specific Configuratio ..
SN74LV595ARGYR ,8-Bit Shift Registers With 3-State Output RegistersFeatures 2 Applications1• 2-V to 5.5-V V Operation • Network SwitchesCC• Max t of 7.1 ns at 5 V • P ..
SN74LV74A ,Dual Positive-Edge-Triggered D-Type Flip-FlopsMaximum Ratingsover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
SN74LV74AD ,Dual Positive-Edge-Triggered D-Type Flip-FlopsElectrical Characteristics....... 511 Layout.... 146.5 Switching Characteristics: V = 2.5 V ± 0.2 V ..
SN74LV74ADBR ,Dual Positive-Edge-Triggered D-Type Flip-FlopsFeatures 3 DescriptionThese dual positive-edge-triggered D-type flip-flops1• 2-V to 5.5-V V Operati ..
SN74LV74ADR ,Dual Positive-Edge-Triggered D-Type Flip-FlopsElectrical Characteristics....... 511 Layout.... 146.5 Switching Characteristics: V = 2.5 V ± 0.2 V ..
SP3243EUCT-L , 3 Driver/5 Receiver Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EUCT-L , 3 Driver/5 Receiver Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EUCT-L , 3 Driver/5 Receiver Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EUCY , High Speed Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EUEA , High Speed Intelligent 3.0V to 5.5V RS-232 Transceivers
SP3243EUEA-L , 3 Driver/5 Receiver Intelligent 3.0V to 5.5V RS-232 Transceivers
SN74LV595AQPWRQ1
Automotive Catalog 8-Bit Shift Registers With 3-State Output Registers
GND
SRCLK
SRCLR
QH′
2-Vto 5.5-V VCC Operation Typical VOLP (Output Ground Bounce) VCC= 3.3V,TA= 25°C Typical VOHV (Output VOH Undershoot) VCC= 3.3V,TA= 25°C Supports Mixed-Mode Voltage Operation
All Ports 8-Bit Serial-In, Parallel-Out Shift Ioff Supports Partial-Power-Down Mode
Operation Shift Register Has Direct Clear
DESCRIPTIONThe SN74LV595Aisan 8-bit shift register designed for 2-Vto 5.5-V VCC operation.
This device contains an 8-bit serial-in, parallel-out register that feeds an 8-bit D-type storage register. The
storage register has parallel 3-state outputs. clocks are provided for both the shift and storage register.
The shift register hasa direct overriding input, serial (SER) input, anda serial output for
cascading. When the output-enable (OE) inputall outputs except QH' arein the high-impedance state.
Both the shift register clock (SRCLK) and register clock (RCLK) are positive-edge triggered.If both
clocks are connected together, the shift registeris one clock pulse aheadof the storage register. ensure the high-impedance state duringor power down, OE shouldbe tiedto VCC througha pullup
