SN74LV393ATPWRQ1 ,Dual 4-Bit Binary CountersSN74LV393A-Q1DUAL 4-BIT BINARY COUNTERSCLS515C − JULY 2003 − REVISED FEBRUARY 2008PW PACKAGE Quali ..
SN74LV4040ADBR ,12-Bit Asynchronous Binary Countersmaximum ratings over operating free-air temperature rangeSupply voltage range, V . . . . . . . . . ..
SN74LV4040ANSR ,12-Bit Asynchronous Binary Countersmaximum ratings over operating free-air temperature rangeSupply voltage range, V . . . . . . . . . ..
SN74LV4040APW ,12-Bit Asynchronous Binary Counters/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74LV4040APWR ,12-Bit Asynchronous Binary Counters SCES226I − APRIL 1999 − REVISED MAY 2005 ..
SN74LV4040APWRG4 ,12-Bit Asynchronous Binary Counter 16-TSSOP -40 to 85maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SP3232EEA , True 3.0V to 5.5V RS-232 Transceivers
SP3232EEA+ , True 3.0V to 5.5V RS-232 Transceivers
SP3232EEA-L , True 3.0V to 5.5V RS-232 Transceivers
SP3232EEA-L , True 3.0V to 5.5V RS-232 Transceivers
SP3232EHCT , 3.3V, 460 Kbps RS-232 Transceivers
SP3232EHCY , 3.3V, 460 Kbps RS-232 Transceivers
SN74LV393ATPWRQ1
Dual 4-Bit Binary Counters
Max tpd of 9.5 ns at 5 V Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down-Mode
Operation Dual 4-Bit Binary Counters With Individual
Clocks Direct Clear for Each 4-Bit Counter Can Significantly Improve System
Densities by Reducing Counter Package
Count by 50 Percent
description/ordering informationThe SN74LV393A contains eight flip-flops and additional gating to implement two individual 4-bit counters in
a single package. This device is designed for 2-V to 5.5-V VCC operation.
This device comprises two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK)
input. The device changes state on the negative-going transition of the CLK pulse. N-bit binary counters can
be implemented with each package, providing the capability of divide by 256. The SN74LV393A has parallel
outputs from each counter stage so that any submultiple of the input count frequency is available for system
timing signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION† For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at http://www.ti.com. Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
FUNCTION TABLEPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1QA
1QB
1QC
1QD
GND
2CLR
2QA
2QB
2QC
2QD
