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SN74LV21ADRTIN/a2124avaiDual 4-Input Positive-AND Gate
SN74LV21APWTIN/a50avaiDual 4-Input Positive-AND Gate
SN74LV21APWRTIN/a1860avaiDual 4-Input Positive-AND Gate


SN74LV21ADR ,Dual 4-Input Positive-AND Gate        SCES340E − SEPTEMBER 2000 − REVISED APRIL 2005SN54L ..
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SN74LV21ADR-SN74LV21APW-SN74LV21APWR
Dual 4-Input Positive-AND Gate
Typical VOHV (Output VOH Undershoot)>2.3 V at VCC = 3.3 V, TA = 25°CIoff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information

These dual 4-input positive-AND gates are
designed for 2-V to 5.5-V VCC operation.
The ’LV21A devices perform the Boolean function�A•B•C• Dor Y�A�B�C� D in
positive logic.
These devices are fully specified for
partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing
damaging current backflow through the devices
when they are powered down.
ORDERING INFORMATION
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
SN54LV21A ...FK PACKAGE
(TOP VIEW)

NC − No internal connection
GND1ANC2A2D
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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