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SN74LV174A-SN74LV174ADR-SN74LV174ANSR-SN74LV174APW-SN74LV174APWR Fast Delivery,Good Price
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SN74LV174ATIN/a706avaiHex D-Type Flip-Flops With Clear
SN74LV174ADRTIN/a10avaiHex D-Type Flip-Flops With Clear
SN74LV174ANSRTIN/a1994avaiHex D-Type Flip-Flops With Clear
SN74LV174APWTIN/a85avaiHex D-Type Flip-Flops With Clear
SN74LV174APWRTIN/a9000avaiHex D-Type Flip-Flops With Clear


SN74LV174APWR ,Hex D-Type Flip-Flops With Clearlogic diagram (positive logic)1CLR9CLK31D1D2C11QRTo Five Other ChannelsPin numbers shown are for th ..
SN74LV174PW , HEX D-TYPE FLIP-FLOPS WITH CLEAR
SN74LV175ANSR ,Quadruple D-Type Flip-Flops With Clearmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LV175APW ,Quadruple D-Type Flip-Flops With Clear       SCLS400G − APRIL 1998 − REVISED APRIL 2005S ..
SN74LV175APWR ,Quadruple D-Type Flip-Flops With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV20AD ,Dual 4-Input Positive-NAND Gatemaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
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SN74LV174A-SN74LV174ADR-SN74LV174ANSR-SN74LV174APW-SN74LV174APWR
Hex D-Type Flip-Flops With Clear
Typical VOHV (Output VOH Undershoot)>2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on
All Ports
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information

The ’LV174A devices are hex D-type flip-flops
designed for 2-V to 5.5-V VCC operation.
These devices are positive-edge-triggered
flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going edge of the
clock pulse. When the clock (CLK) input is at
either the high or low level, the D-input signal has
no effect at the output.
ORDERING INFORMATION
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV174A... FK PACKAGE
(TOP VIEW)
CLRNC
CLK
GND
GND
CLK
NC − No internal connection
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