SN54LS393J ,DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTERSN54/74LS390SN54/74LS393DUAL DECADE COUNTER;DUAL 4-STAGEBINARY COUNTERDUAL DECADE COUNTER;The SN54/ ..
SN54LS395 ,4-BIT SHIFT REGISTER WITH 3-STATE OUTPUTSSN74LS3954-BIT SHIFT REGISTERWITH 3-STATE OUTPUTSThe SN74LS395 is a 4-Bit Register with 3-state out ..
SN54LS395AJ ,4-BIT CASCADABLE SHIFT REFISTERS WITH 3-STATE OUTPUTS
SN54LS395AJ. ,4-BIT CASCADABLE SHIFT REFISTERS WITH 3-STATE OUTPUTS
SN54LS395J ,4-bit shift register with 3-state outputsSN74LS3954-BIT SHIFT REGISTERWITH 3-STATE OUTPUTSThe SN74LS395 is a 4-Bit Register with 3-state out ..
SN54LS395J ,4-bit shift register with 3-state outputsSN74LS3954-BIT SHIFT REGISTERWITH 3-STATE OUTPUTSThe SN74LS395 is a 4-Bit Register with 3-state out ..
SN74HC125NSR ,Quadruple Bus Buffer Gates With 3-State OutputsLogic Diagram (Positive Logic)1 101OE 3OE2 3 9 81A 1Y 3A 3Y4 132OE 4OE5 6 12 112A 2Y 4A 4YPin numbe ..
SN74HC125NSRG4 ,Quadruple Bus Buffer Gates With 3-State Outputs 14-SO -40 to 85Maximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74HC125PWR ,Quadruple Bus Buffer Gates With 3-State Outputs 14-TSSOP -40 to 85Maximum Ratings.. 49 Application and Implementation...... 116.2 ESD Ratings ...... 49.1 Application ..
SN74HC126 ,Quadruple Bus Buffer Gates With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HC126D ,Quadruple Bus Buffer Gates With 3-State Outputs SCLS103E − MARCH 1984 − REVISED JULY 200 ..
SN74HC126DB , QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
74LS393-SN54LS390J-SN54LS393J-SN74LS390N-SN74LS393D-SN74LS393N
Dual 4-Bit Binary Counter
DUAL DECADE COUNTER;
DUAL 4-STAGE
BINARY COUNTERThe SN54/74LS390 and SN54/74LS393 each contain a pair of high-speed
4-stage ripple counters. Each half of the LS390 is partitioned into a
divide-by-two section and a divide-by five section, with a separate clock input
for each section. The two sections can be connected to count in the 8.4.2.1
BCD code or they can count in a biquinary sequence to provide a square wave
(50% duty cycle) at the final output.
Each half of the LS393 operates as a Modulo-16 binary divider, with the last
three stages triggered in a ripple fashion. In both the LS390 and the LS393,
the flip-flops are triggered by a HIGH-to-LOW transition of their CP inputs.
Each half of each circuit type has a Master Reset input which responds to a
HIGH signal by forcing all four outputs to the LOW state. Dual Versions of LS290 and LS293 LS390 has Separate Clocks Allowing ÷2, ÷2.5, ÷5 Individual Asynchronous Clear for Each Counter Typical Max Count Frequency of 50 MHz Input Clamp Diodes Minimize High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
SN54/74LS390
SN54/74LS393NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.- - -- - -- -- -- -- - -- -- -------- - -- ---- --- - -- -- -- ---
