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74LS196-74LS197-SN54LS196J-SN54LS197J-SN74LS197N
4-STAGE PRESETTABLE RIPPLE COUNTERS
4-STAGE PRESETTABLE
RIPPLE COUNTERSThe SN54/74LS196 decade counter is partitioned into divide-by-two and di-
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)
sequence or in a bi-quinary mode producing a 50% duty cycle output. The
SN54/74LS197 contains divide-by-two and divide-by-eight sections which
can be combined to form a modulo-16 binary counter. Low Power Schottky
technology is used to achieve typical count rates of 70 MHz and power dis-
sipation of only 80 mW.
Both circuit types have a Master Reset (MR) input which overrides all other
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)
overrides clocked operations and asynchronously loads the data on the Par-
allel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits
usable as programmable counters. The circuits can also be used as 4-bit
latches, loading data from the Parallel Data inputs when PL is LOW and stor-
ing the data when PL is HIGH. Low Power Consumption — Typically 80 mW High Counting Rates — Typically 70 MHz Choice of Counting Modes — BCD, Bi-Quinary, Binary Asynchronous Presettable Asynchronous Master Reset Easy Multistage Cascading Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)- - -- -- -- -- -- -- -- -- -- ---
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES LOADING (Note a)CP0 Clock (Active LOW Going Edge)
Input to Divide-by-Two Section
CP1 (LS196) Clock (Active LOW Going Edge)
Input to Divide-by-Five Section
CP1 (LS197) Clock (Active LOW Going Edge)
Input to Divide-by-Eight Section Master Reset (Active LOW) Input Parallel Load (Active LOW) Input
P0–P3 Data Inputs
Q0–Q3 Outputs (Notes b, c)
NOTES:
a. 1 TTL Unit Load (U.L.) = 40μA HIGH/1.6 mA LOW.
