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SN74LS166ML1N/a1000avai8-Bit Shift Registers
SN74LS166ML1MOTORMLN/a935avai8-Bit Shift Registers
SN74LS166ML1MOTN/a1000avai8-Bit Shift Registers
SN74LS166MR1MOTN/a1000avai8-Bit Shift Registers


SN74LS166ML1 ,8-Bit Shift Registers
SN74LS166ML1 ,8-Bit Shift Registers
SN74LS166ML1 ,8-Bit Shift Registers
SN74LS166MR1 ,8-Bit Shift Registers
SN74LS169N ,BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERSLOGIC DIAGRAMSSN54/74LS168P P P P0 1 2 3PECEPCETU/D TCCPCP DQ Q Q Q0 1 2 3FAST AND LS TTL DATA5-2SN ..
SN74LS170N ,4 x 4 REGISTER FILE OPEN-COLLECTORSN54/74LS1704 x 4 REGISTER FILEOPEN-COLLECTORThe TTL /MSI SN54 /74LS170 is a high-speed, low-power ..
SOC100A , THIN FILM COMPENSATED SENSORS
SOC100A , THIN FILM COMPENSATED SENSORS
SOC100A , THIN FILM COMPENSATED SENSORS
SOD4002 ,Conductor Holdings Limited - PLASTIC SILICON RECTIFIER
SOD4004 ,Conductor Holdings Limited - PLASTIC SILICON RECTIFIER
SOD4004 ,Conductor Holdings Limited - PLASTIC SILICON RECTIFIER


SN74LS166ML1-SN74LS166MR1
8-Bit Shift Registers
--The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs
buffered, the drive requirements are lowered to one 74LS standard
load. By utilizing input clamping diodes, switching transients are
minimized and system design simplified.
The LS166 is a parallel-in or serial-in, serial-out shift register and
has a complexity of 77 equivalent gates with gated clock inputs and an
overriding clear input. The shift/load input establishes the parallel-in
or serial-in mode. When high, this input enables the serial data input
and couples the eight flip-flops for serial shifting with each clock
pulse. Synchronous loading occurs on the next clock pulse when this is
low and the parallel data inputs are enabled. Serial data flow is
inhibited during parallel loading. Clocking is done on the low-to-high
level edge of the clock pulse via a two input positive NOR gate, which
permits one input to be used as a clock enable or clock inhibit function.
Clocking is inhibited when either of the clock inputs are held high,
holding either input low enables the other clock input. This will allow
the system clock to be free running and the register stopped on
command with the other clock input. A change from low-to-high on
the clock inhibit input should only be done when the clock input is
high. A buffered direct clear input overrides all other inputs, including
the clock, and sets all flip-flops to zero. Synchronous Load Direct Overriding Clear Parallel to Serial Conversion
GUARANTEED OPERATING RANGES
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