SN74LS132MR1 ,Quad 2-Input Schmitt Trigger NAND Gate
SN74LS132N ,QUAD 2-INPUT SCHMITT TRIGGER NAND GATEmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74LS132NSR ,Quad 2-input positive-NAND Schmitt triggerslogic diagram (positive logic)1A _CCC-Dr-------"IB2ACIIiDr-----2Y2B3A_rii-) 3Y3B4ACrrCii)y-----4y4B ..
SN74LS137 ,3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES
SN74LS138 ,LOW POWER SCHOTTKY
SN74LS138DR2 ,1-OF-8 Decoder/ Demultiplexerallow parallel expansion to a 1-of-24 decoder using just three LS138devices or to a 1-of-32 decoder ..
SNJ54LS42J , 54LS42 DM54LS42 DM74LS42 BCD to Decimal Decoders
SNJ54LS47J ,BCD-to-Seven-Segment Decoders/Drivers
SNJ54LS47J ,BCD-to-Seven-Segment Decoders/Drivers
SNJ54LS540J ,Octal Buffers And Line Drivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SNJ54LS541J ,Octal Buffers And Line Drivers With 3-State Outputslogic diagram (positive logic)'LS540 'LSS41absolute
SNJ54LS54J ,4-Wide AND-OR-invert Gateslogic diagrams (positive logic)SN5454 . . . J PACKAGESN7454 . . . N PACKAGE(TOP VIEW)SN5454 . . . W ..
SN74LS132MR1
Quad 2-Input Schmitt Trigger NAND Gate
----The SN74LS132 contains four 2-Input NAND Gates which accept
standard TTL input signals and provide standard TTL output levels.
They are capable of transforming slowly changing input signals into
sharply defined, jitter-free output signals. Additionally, they have
greater noise margin than conventional NAND Gates.
Each circuit contains a 2-input Schmitt trigger followed by a
Darlington level shifter and a phase splitter driving a TTL totem pole
output. The Schmitt trigger uses positive feedback to effectively
speed-up slow input transitions, and provide different input threshold
voltages for positive and negative-going transitions. This hysteresis
between the positive-going and negative-going input thresholds
(typically 800 mV) is determined internally by resistor ratios and is
essentially insensitive to temperature and supply voltage variations.
As long as one input remains at a more positive voltage than VT+
(MAX), the gate will respond to the transitions of the other input as
shown in Figure 1.
VCC
GND
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)
GUARANTEED OPERATING RANGES
