SN74HCT623N ,Octal Bus Transceivers With 3-State Outputs SN54HCT623, SN74HCT623 OCTAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCLS016C – MARCH 1984 – REVISED M ..
SN74HCT645DW ,Octal Bus Transceivers With 3-State Outputs SCLS019D − MARCH 1984 − REVISED AUGUS ..
SN74HCT646DW ,Octal Bus Transceivers And Registers With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HCT646NT , OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74HCT652 ,Octal Bus Transceivers And Registers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HCT652DW ,Octal Bus Transceivers And Registers With 3-State Outputslogic diagram (positive logic)21OEBA3OEAB23CLKBA22SBA1CLKAB2SABOne of Eight Channels1DC14A120B11DC1 ..
SNJ5451W ,AND-OR-invert Gates
SNJ5454J ,4-Wide AND-OR-invert GatesSDLS115SN5454. SN54LS54. SN7454. SN74LS§44-WIDE MliMWllll1lERT GATESDECEMBER 1983-REViSED MARCH 198 ..
SNJ5472J ,And-Gated J-K Master-Slave Flip-Flops With Preset And Clearlogic diagram (positive logic)CLKschematics of inputs and outputsEQUIVALENT OF EACH INPUT TYPICAL O ..
SNJ5472W ,And-Gated J-K Master-Slave Flip-Flops With Preset And Clearlogic diagram (positive logic)CLKschematics of inputs and outputsEQUIVALENT OF EACH INPUT TYPICAL O ..
SNJ5474W , DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
SNJ5486J ,Quadruple 2-Input Exclusive-OR Gates
SN74HCT623N
Octal Bus Transceivers With 3-State Outputs
Low Input Current of 1 μA MaxTo 15 LSTTL Loads
description/ordering informationThese octal bus transceivers are designed for asynchronous two-way communication between data buses. The
control-function implementation allows for maximum flexibility in timing.
The ’HCT623 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus,
depending upon the logic levels at the output-enable (OEAB and OEBA) inputs.
The output-enable inputs disable the device so that the buses are effectively isolated. The dual-enable
configuration gives the transceivers the capability to store data by simultaneously enabling OEAB and OEBA.
Each output reinforces its input in this transceiver configuration. When both OEAB and OEBA are enabled and
all other data sources to the two sets of bus lines are in the high-impedance state, both sets of bus lines (16 total)
remain at their last states. The 8-bit codes appearing on the two sets of buses are identical.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking/current-sourcing capability of the driver.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
