SN74HCT373PWR ,Octal Transparent D-Type Latches With 3-State OutputsSN54HCT373, SN74HCT373OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCLS009D – MARCH 1984 – R ..
SN74HCT373PWR ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT373PWR ,Octal Transparent D-Type Latches With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HCT374 ,Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HCT374DBRG4 ,Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-SSOP -40 to 85 SCLS005D − MARCH 1984 − ..
SN74HCT374DW ,Octal D-type Edge-Triggered Flip-Flops With 3-State Outputslogic diagram (positive logic)1OE11CLKC121Q31D1DTo Seven Other Channels†absolute
SNJ54153J ,Dual 4-Line To 1-Line Data Selectors/Multiplexers
SNJ54153J ,Dual 4-Line To 1-Line Data Selectors/Multiplexers
SNJ54154J ,4-Line To 16-Line Decoders/Demultiplexers
SNJ54157J ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SNJ54157J ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SNJ54157J ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SN74HCT373-SN74HCT373DW-SN74HCT373DWR-SN74HCT373N-SN74HCT373NSR-SN74HCT373PW-SN74HCT373PWR
Octal Transparent D-Type Latches With 3-State Outputs
-
Typical tpd = 21 ns ±6-mA Output Drive at 5 V
Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible Eight High-Current Latches in a SinglePackage Full Parallel Access for Loading
description/ordering informationThese 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches of the ’HCT373 devices are
transparent D-type latches. While the
latch-enable (LE) input is high, the Q outputs
follow the data (D) inputs. When LE is taken low,
the Q outputs are latched at the levels that were
set up at the D inputs.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.1QOE8Q
GND
SN54HCT373.. .FK PACKAGE
(TOP VIEW)GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
