SN74HC563N ,Octal Transparent D-Type Latches With 3-State Outputs SN54HC563, SN74HC563 OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCLS145C – DECEMBER 1982 ..
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SN74HC573A ,Octal Transparent D-Type Latches With 3-State OutputsBlock Diagram... 10Information..... 134 Revision HistoryNOTE: Page numbers for previous revisions m ..
SN74HC573ADW ,Octal Transparent D-Type Latches With 3-State OutputsLogic Diagram (Positive Logic)1OE11LEC1191Q21D1DTo Seven Other ChannelsCopyright 2016, Texas Instr ..
SN74HC573ADWR ,Octal Transparent D-Type Latches With 3-State OutputsSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54HC573A,SN74HC573 ..
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SN74HC563N
Octal Transparent D-Type Latches With 3-State Outputs
GND
SN54HC563 ...J OR W PACKAGE
SN74HC563... DW OR N PACKAGE
(TOP VIEW)
SN54HC563... FK PACKAGE
(TOP VIEW)1DOE7Q
GND
description/ordering informationThese 8-bit transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive
or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When
LE is taken low, the outputs are latched at the inverses of the levels set up at the D inputs.
A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines
without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
