SN74HC161DR ,4-Bit Synchronous Binary Counterslogic diagram, each D/T flip-flop (positive logic)CKLDTE†TGLDTGQTG†LD TG†CKD†CKTG TG††CKCKR†The ori ..
SN74HC161N ,4-Bit Synchronous Binary Counterslogic diagram. The uses of these signals are shownon the
SN74HC161NE4 ,4-Bit Synchronous Binary Counters 16-PDIP -40 to 85logic diagram of the D/T flip-flops.Pin numbers shown are for the D, J, N, NS, PW, and W packages.3 ..
SN74HC161NSR ,4-Bit Synchronous Binary Counters/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HC163DR , 4-BIT SYNCHRONOUS BINARY COUNTERS
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SN75C189ADR ,Quadruple Low-Power Line Receivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN75C189ADRE4 ,Quadruple Low-Power Line Receiver 14-SOIC 0 to 70maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN75C189ADRG4 ,Quadruple Low-Power Line Receiver 14-SOIC 0 to 70maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75C189AN ,Quadruple Low-Power Line Receiverlogic diagram (each receiver)A Y11AResponse2 3THRESHOLD1 CONT 1YControlADJUST42A562 CONT2Y103A893Y3 ..
SN75C189ANSR ,Quadruple Low-Power Line Receivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75C189ANSRG4 ,Quadruple Low-Power Line Receiver 14-SO 0 to 70maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HC161-SN74HC161D-SN74HC161DG4-SN74HC161DR-SN74HC161N-SN74HC161NE4-SN74HC161NSR
4-Bit Synchronous Binary Counters
±4-mA Output Drive at 5 V
Synchronously ProgrammableSN54HC161 ...J OR W PACKAGE
SN74HC161... D, N, NS, OR PW PACKAGE
(TOP VIEW)C
SN54HC161... FK PACKAGE
(TOP VIEW)CLKCLRNC
LOAD
ENT
RCO
ENP
GND
CLR
CLK
ENP
GNDCC
RCOB
ENT
LOAD
NC − No internal connection
description/ordering informationThese synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. The ’HC161 devices are 4-bit binary counters. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed
by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output
counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK)
input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
