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SN74HC112-SN74HC112D-SN74HC112DR-SN74HC112N
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Maxdescription/ordering informationThe ’HC112 devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the fall time of the
CLK pulse. Following the hold-time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops perform as toggle flip-flops by tying J and
K high.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
2CLR
2CLK
1PRE1CLKNC1CLR
GND
SN54HC112... FK PACKAGE
(TOP VIEW)NC − No internal connection
1PRE
GND
2CLR
2CLK
2PRE
2PRE
