SN74HC109N ,Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset SCLS470A − MARCH ..
SN74HC10D ,Triple 3-Input Positive-NAND Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HC10DR ,Triple 3-Input Positive-NAND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HC10N ,Triple 3-Input Positive-NAND Gateslogic diagram (positive logic)AYBC†absolute
SN74HC10NSR ,Triple 3-Input Positive-NAND Gates SCLS083D − DECEMBER 1982 − REVISED AUGUST 2003 Wide ..
SN74HC10PW ,Triple 3-Input Positive-NAND Gateslogic diagram (positive logic)AYBC†absolute
SN75970B2DGG ,SCSI Differential Converter Control
SN75970B2DGG ,SCSI Differential Converter Control
SN75970B2DL ,SCSI Differential Converter Control
SN75970B2DL ,SCSI Differential Converter Control
SN75971B1DL ,SCSI Differential Converter-DataSN75971BSCSI DIFFERENTIAL CONVERTER-DATASLLS322A – NOVEMBER 1999 – REVISED JANUARY 2000* Provides ..
SN75971B2DGG ,SCSI Differential Converter-DataSN75971BSCSI DIFFERENTIAL CONVERTER-DATASLLS322A – NOVEMBER 1999 – REVISED JANUARY 2000* Provides ..
SN74HC109DR-SN74HC109N
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset
SN54HC109 ...J OR W PACKAGE
SN74HC109... D, N, OR NS PACKAGE
(TOP VIEW)1CLR
1CLK
1PRE
GND
VCC
2CLR
2CLK
2PRE
SN54HC109... FK PACKAGE
(TOP VIEW)NC − No internal connection
2CLK
2PRE
1CLK
1PRE1CLRNC2Q2CLR
GND
description/ordering informationThese devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE)
or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR
are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related
directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be
changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by
grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
