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SN74GTLPH16912TIN/a81avai18-Bit LVTTL-to-GTLP Universal Bus Transceiver
SN74GTLPH16912GRTEXASN/a4avai18-Bit LVTTL-to-GTLP Universal Bus Transceiver


SN74GTLPH16912 ,18-Bit LVTTL-to-GTLP Universal Bus TransceiverFEATURESDGG OR DGV PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)FamilyOEAB 1 56 CEAB• ..
SN74GTLPH16912GR ,18-Bit LVTTL-to-GTLP Universal Bus TransceiverFUNCTIONAL DESCRIPTIONThe SN74GTLPH16912 is a medium-drive (50-mA), 18-bit UBT transceiver containi ..
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SN74GTLPH16912-SN74GTLPH16912GR
18-Bit LVTTL-to-GTLP Universal Bus Transceiver
FEATURES DGG OR DGV PACKAGE
(TOP VIEW)

OEAB
LEAB
GND
VCC
GND
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
CEAB
CLKAB
GND
BIAS VCC
GND
B10
B11
B12
GND
B13
B14
B15
VREF
B16
B17
GND
B18
CLKBA
CEBA
DESCRIPTION/ORDERING INFORMATION
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
Memberof Texas Instruments Widebus™
Family
UBT™ Transceiver Combines D-Type Latches
and D-Type for Operationin
Transparent, Clocked, and
Clock-Enabled Modes
TI-OPC™ Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Bidirectional Between GTLP Signal
Levels and Logic Levels
LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) LVTTL Outputs (–24 mA/24 mA) GTLP Rise Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrityin Loads
Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
Bus Hold on Data Inputs Distributed and GND Pins Minimize
High-Speed Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII
ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
The SN74GTLPH16912isa medium-drive, 18-bit UBT™ transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL translation.It allows for transparent, latched, clocked, and clock-enabled modesof
data transfer. The device providesa high-speed interface cards operatingat LVTTL logic levels anda
backplane operatingat GTLP signal levels. High-speed (about three times faster than standard TTLor LVTTL)
backplane operationisa direct resultof GTLP's reduced swing (<1 V), reduced input threshold levels,
improved differential input, OEC™ circuitry, and TI-OPC™ Improved GTLP OEC and TI-OPC circuits
minimize bus-settling time and have been designed and tested using several backplane models. The medium allows incident-wave switchingin heavily loaded backplanes with equivalent load impedance downto19Ω. Texas Instruments (TI™) derivativeof the Transceiver Logic (GTL) JEDEC standard Theof the SN74GTLPH16912 given onlyat the preferred higher noise-margin but user flexibilityof using this deviceat GTL(VTT= 1.2V andVREF= 0.8V)or GTLP 1.5 and=
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