SN74GTLPH1655DGGR ,16-Bit LVTTL-To-GTLP Adjustable-Edge-Rate Universal Bus TransceiverFEATURESDGG PACKAGE• Member of Texas Instruments' Widebus™(TOP VIEW)Family1 641OEAB CLK• UBT™ Trans ..
SN74GTLPH16912 ,18-Bit LVTTL-to-GTLP Universal Bus TransceiverFEATURESDGG OR DGV PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)FamilyOEAB 1 56 CEAB• ..
SN74GTLPH16912GR ,18-Bit LVTTL-to-GTLP Universal Bus TransceiverFUNCTIONAL DESCRIPTIONThe SN74GTLPH16912 is a medium-drive (50-mA), 18-bit UBT transceiver containi ..
SN74GTLPH306PW ,8-Bit LVTTL-to-GTLP Bus Transceiverfeatures TI-OPC circuitry, which actively limits overshoot caused by improperly terminatedbackplane ..
SN74GTLPH306PWR ,8-Bit LVTTL-to-GTLP Bus TransceiverFEATURESDGV, DW, OR PW PACKAGE• TI-OPC™ Circuitry Limits Ringing on(TOP VIEW)Unevenly Loaded Backpl ..
SN74H01J , QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS
SN752232 , DUAL RS-232 PORT
SN752232DL , DUAL RS-232 PORT
SN75240 ,Dual USB Port Transient SuppressorMaximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
SN75240P ,Dual USB Port Transient SuppressorSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN65220,SN65240,SN75 ..
SN75240PW ,Dual USB Port Transient SuppressorMaximum Ratings.. 413.2 Layout Example....... 108.2 ESD Ratings........ 414 Device and Documentatio ..
SN75240PWG4 ,Dual USB Port Transient Suppressor 8-TSSOP 0 to 70Electrical Characteristics....... 414.3 Trademarks..... 118.6 Typical Characteristics. 514.4 Electr ..
SN74GTLPH1655DGGR
16-Bit LVTTL-To-GTLP Adjustable-Edge-Rate Universal Bus Transceiver
FEATURES DGG PACKAGE
(TOP VIEW)1OEAB
1OEBA
VCC
1A1
GND
1A2
1A3
GND
1A4
GND
1A5
GND
1A6
1A7
VCC
1A8
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
2A6
GND
2A7
VCC
2A8
GND
2OEAB
2OEBA
CLK
1LEAB
1LEBA
ERC
GND
1B1
1B2
GND
1B3
1B4
1B5
GND
1B6
1B7
VCC
1B8
2B1
GND
2B2
2B3
GND
2B4
2B5
VREF
2B6
GND
2B7
2B8
BIAS VCC
2LEAB
2LEBA
DESCRIPTION Memberof Texas Widebus™
Family UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operationin
Transparent, Latched,or Clocked Modes TI-OPC™ Circuitry Limits Ringing on
Unevenly Loaded OEC™ Circuitry Signal Integrity and
Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels Partitionedas Two 8-Bit Transceivers With
Individual Latch and Output Control,
but Witha Common Clock LVTTL Interfaces 5-V Tolerant High-Drive GTLP (100 mA) LVTTL Outputs mA/24 mA) Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
Data-Transfer Rate and Signal Integrityin
Distributed Loads Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC GND Pins Minimize
High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class ESD Protection JESD22 2000-V Human-Body Model (A114-A) 200-V Machine (A115-A) 1000-V Charged-Device Model (C101)The SN74GTLPH1655 isa high-drive, 16-bit UBT™ transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation.Itis partitioned as two transceivers and allows for transparent,
latched, and clockedof data transfer. The device providesa high-speed interface between cards
operatingat LVTTL levels anda backplane operatingat GTLP signal levels. High-speed (about three times than standardor TTL) backplane operationisa resultof GTLP's reduced output swing V), input threshold levels, improved differential OEC™ circuitry, and TI-OPC™ circuitry. OEC TI-OPC circuits minimize bus-settling and have been designed and tested using backplane The high drive allows incident-wave switchingin heavily loaded backplanes with impedanceΩ.
