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SN74GTL2010PWRTIN/a150avai10-Bit Voltage Clamp 24-TSSOP -40 to 85


SN74GTL2010PWR ,10-Bit Voltage Clamp 24-TSSOP -40 to 85FEATURESPW PACKAGE• Provides Bidirectional Voltage Translation(TOP VIEW)With No Direction Control R ..
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SN74GTLP1394PW ,2-Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvr w/Split LVTTL Port, Feedback Path, & Selectable Polarityfeatures TI-OPC circuitry, which actively limits the overshoot caused by improperly terminatedbackp ..
SN74GTLP1394PWR ,2-Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvr w/Split LVTTL Port, Feedback Path, & Selectable PolaritySCES286F–OCTOBER 1999–REVISED APRIL 2005DESCRIPTION/ORDERING INFORMATION (CONTINUED)The SN74GTLP139 ..
SN75196 ,Multiple RS-232 Driver And Receiverlogic diagram (positive logic)2 191DA 1DY3 182DA 2DY4 173DA 3DY5 161RY 1RA6 152RY 2RA7 144DA 4DY8 1 ..
SN75196DW ,Multiple RS-232 Driver And Receivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage, V (see ..
SN75196DWR ,Multiple RS-232 Driver And Receivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage, V (see ..
SN75207BD ,Dual High-Sensitivity Line RECmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN75207BN ,Dual High-Sensitivity Line RECfeatures a TTL-compatible, active-pullup output.Input protection diodes are in series with the coll ..
SN752232 , DUAL RS-232 PORT


SN74GTL2010PWR
10-Bit Voltage Clamp
FEATURES 13
SREF
GREF
DREF
D10
APPLICATIONS
DESCRIPTION/ORDERING INFORMATION PACKAGE
Provides Voltage Translation (TOP VIEW)
With No Control Required
Allows Translation From1V up5V Provides With GTL, GTL+,
LVTTL/TTL, 5-V CMOS Levels
Low On-State Between Input and
Output
Supports Hot Insertion No Power Required– Will Not Latch 5-V-Tolerant Low Standby Flow-Through Pinout for Easeof Printed
Circuit Routing
ESD Protection JESD22 2000-V Model (A114-4) 1000-V Charged-Device Model (C101) Bidirectional Applications
Requiring Translation From
Any Voltage(1Vto5V)to Any Voltage(1V5V)
Low VoltageI2C Port Translation 3.3-VI2C Bus Signal Levels GTL/GTL+to LVTTL/TTL Signal
Levels

The GTL2010 ten NMOS pass transistors (Sn and Dn) with gate (GREF) anda reference
transistor (SREF DREF). The low ON-state resistanceof the switch connectionsto be made with
minimal propagation delay. With no direction control pin required, allows bidirectional voltage
translations any voltage(1Vto5V)to any voltage(1Vto5 V).
When the Snis LOW, the clampisin the ON state and connection exists between
the Sn and Assuming the higher voltageis on the Dn port, Dn portis HIGH, the voltageon
the Sn port the voltage setby the reference transistor (SREF). the Sn portis HIGH, the Dn port pulledto VCC pullup resistors.
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