SN74F125DR ,Quadruple Bus Buffer Gate With 3-State Outputslogic diagram (positive logic)11OE231A 1Y42OE562A 2Y103OE983A 3Y134OE12 114A 4Y†absolute
SN74F125DRG4 ,Quadruple Bus Buffer Gate With 3-State Outputs 14-SOIC 0 to 70maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F125N ,Quadruple Bus Buffer Gate With 3-State Outputs SN74F125 QUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTSSDFS016B – JANUARY 1989 – REVISED JULY 2002D ..
SN74F125NSR ,Quadruple Bus Buffer Gate With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74F126D ,Quadruple Bus Buffer Gate With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74F126DR ,Quadruple Bus Buffer Gate With 3-State Outputs/sc/package.FUNCTION TABLE(each buffer)INPUTSOUTPUTYOE AH H HH LLL X ZPlease be aware that an impor ..
SN751178N ,Dual Differential Driver/Receiver Pairslogic diagrams (positive logic)logic symbolsSN751177 SN7511771212DE EN1DE4EN2RE414 RE1Y15 11D 14131 ..
SN751178NSR ,Dual Differential Driver/Receiver Pairsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN75117P ,Differential Line Transreceiverlogic diagram (positive logic)logic symbol‡’116‡’116 and SN75118& 4DYP1313 3DE EN DYS DE14 1 4DA D ..
SN75117P ,Differential Line Transreceiverfeatures a differential-input circuit having acommon-mode voltage range of ±15 V. An internal 130-Ω ..
SN75118 ,Differential Line Transceiverlogic diagram (positive logic)logic symbol‡’116‡’116 and SN75118& 4DYP1313 3DE EN DYS DE14 1 4DA D ..
SN75118N ,Differential Line Transceiverfeatures a differential-input circuit having acommon-mode voltage range of ±15 V. An internal 130-Ω ..
SN74F125-SN74F125D-SN74F125DR-SN74F125DRG4-SN74F125N-SN74F125NSR
Quadruple Bus Buffer Gate With 3-State Outputs
description/ordering informationThe SN74F125 features independent line drivers
with 3-state outputs. Each output is disabled when
the associated output-enable (OE) input is high.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each buffer)Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2OE
GND
3OE
