SN74CBT3257CDBQR ,4-Bit 1-Of-2 FET Multiplexer/Demultiplexer with -2 V Undershoot Protectionlogic diagram (positive logic)4 21A SW 1B131B2SW7 52A SW 2B162B2SW9 113A SW 3B1103B2SW12 144A SW 4B ..
SN74CBT3257CDBR ,4-Bit 1-Of-2 FET Multiplexer/Demultiplexer with -2 V Undershoot Protection/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74CBT3257CDG4 ,4-Bit 1-Of-2 FET Multiplexer/Demultiplexer with -2 V Undershoot Protection 16-SOIC -40 to 85 ..
SN74CBT3257CDR ,4-Bit 1-Of-2 FET Multiplexer/Demultiplexer with -2 V Undershoot Protectionmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74CBT3257CDRG4 ,4-Bit 1-Of-2 FET Multiplexer/Demultiplexer with -2 V Undershoot Protection 16-SOIC -40 to 85 ..
SN74CBT3257CPW ,4-Bit 1-Of-2 FET Multiplexer/Demultiplexer with -2 V Undershoot Protection ..
SN74S132N ,Quad 2-input positive-NAND Schmitt triggers
SN74S134 ,12-INPUT POSITIVE-NAND GATES WITH 3-STATE OUTPUTS
SN74S134N ,12-input positive-NAND gates with 3-state outputs
SN74S140D ,Dual 4-input positive-NAND 50-Ohm line drivers. Package Options Include Ceramic ChipCarriers and Flat Packages in Addition toPlastic and Ceramic ..
SN74S140N ,Dual 4-input positive-NAND 50-Ohm line driverslogic diagram (each driver)1AIB 1V"ID2A2B 2Y2C20logic symbol t(1)IA1B1CID2AtThis symbol is in accor ..
SN74S140NSR ,Dual 4-input positive-NAND 50-Ohm line drivers. Package Options Include Ceramic ChipCarriers and Flat Packages in Addition toPlastic and Ceramic ..
SN74CBT3257CDBQR-SN74CBT3257CDBR-SN74CBT3257CDG4-SN74CBT3257CDR-SN74CBT3257CDRG4-SN74CBT3257CPW-SN74CBT3257CPWG4-SN74CBT3257CPWR
4-Bit 1-Of-2 FET Multiplexer/Demultiplexer with -2 V Undershoot Protection
Characteristics (ron = 3 Ω Typical) Low Input/Output Capacitance Minimizes
Loading and Signal Distortion io(OFF) = 5.5 pF Typical) Data and Control Inputs Provide
Undershoot Clamp Diodes Low Power ConsumptionCC = 3 µA Max) VCC Operating Range From 4 V to 5.5 V Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode
Operation Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101) Supports I2C Bus Expansion Supports Both Digital and Analog
Applications: USB Interface, Bus Isolation,
Low-Distortion Signal Gating
description/ordering information
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
RGY PACKAGE
(TOP VIEW)4B1
4B2
3B1
3B2
1B1
1B2
2B1
2B2
GND
1B2
2B1
2B2
GND
4B1
4B2
3B1
3B2
