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SN74BCT646DW
Octal Bus Transceivers And Registers
SN54BCT646, SN74BCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS037D − AUGUST 1989 − REVISED MAY 2004
State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ Bus Transceivers/Registers Independent Registers and Enables for
A and B Buses Multiplexed Real-Time and Stored Data ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)CLKAB
SAB
DIR
GND
VCC
CLKBA
SBA
SN54BCT646 ...JT OR W PACKAGE
SN74BCT646... DW OR NT PACKAGE
(TOP VIEW)4321 2813141516
SN54BCT646...FK PACKAGE
(TOP VIEW)DIRSABCLKABB7A8
GND CLKBASBAV B61826
NC − No internal connection
description/ordering informationThese devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the ’BCT646 devices.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port can be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),
A data can be stored in one register and/or B data can be stored in the other register.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
