SN74BCT29854DW ,8-Bit To 9-Bit Parity Transceivers SCBS257 − SEPTEMBER 1987 − REVISED NOVEMBER 1993DW ..
SN74BCT29854NT , 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
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SN74BCT29854DW
8-Bit To 9-Bit Parity Transceivers
ERR
CLR
GND
PARITY
OEB
Opposite Side From Outputs) Functionally Equivalent to AMD Am29854 High-Speed Bus Transceiver With Parity
Generator/Checker Parity-Error Flag With Open-Collector
Output Latch for Storage of the Parity-Error Flag Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
descriptionThe SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not
an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device
so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with an open-collector parity-error (ERR) flag. ERR can be either passed, sampled, stored, or cleared from the
latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is
transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition
which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C.
FUNCTION TABLENA = not applicable, NC = no change, X = don’t care
†Summation of low-level inputs includes PARITY along with Bi inputs.
‡Output states shown assume the ERR output was previously high.
§In this mode, the ERR output, when enabled, shows noninverted parity of the A bus.
