SN74AVC8T245DGVR ,8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State OutputsFeatures 3 DescriptionThis 8-bit noninverting bus transceiver uses two1• Latch-Up Performance Excee ..
SN74AVC8T245PW ,8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State OutputsMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV , ..
SN74AVC8T245PWR ,8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State OutputsLogic Diagram (Positive Logic) CC CCinput is at GND, both ports are in the high-impedancestate.2DIR ..
SN74AVC8T245RHLR ,8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State OutputsElectrical Characteristics and all Switching Characteristics tables.. 6A• Added Documentation Suppo ..
SN74AVCA164245GR ,16-Bit Dual-Supply Bus Transceive W/Configurable Voltage Translation and 3-StateMaximum Ratingsover operating free-air temperature range (unless otherwise noted)MIN MAX UNITVCCASu ..
SN74AVCA164245KR ,16-Bit Dual-Supply Bus Transceive W/Configurable Voltage Translation and 3-StateSCES395B–JULY 2002–REVISED OCTOBER 2005TERMINAL ASSIGNMENTSDGG OR DGV PACKAGE(TOP VIEW)1 481DIR 1OE ..
SN74LVT8980ADW ,Embedded Test-Bus Controllers IEEE STD 1149.1 (JTAG) TAP Masters W/ 8-Bit Generic Host Interfacesfeatures ensure that virtually any IEEE Std 1149.1 target device or device chain can be serviced by ..
SN74LVT8980ADWR ,Embedded Test-Bus Controllers IEEE STD 1149.1 (JTAG) TAP Masters W/ 8-Bit Generic Host Interfaces/sc/package. %-/(0+.#%(- )(-),0-& 10('*)#& %- #$, /(0+.#%9, (0',&%7- 1$.&, (/ ',9,3( ..
SN74LVT8980ADWRG4 ,Embedded Test-Bus Controllers IEEE STD 1149.1 (JTAG) TAP Masters W/ 8-Bit Generic Host Interfaces 24-SOIC -40 to 85 ! ..
SN74LVT8980DW , EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SN74LVT8980DW , EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SN74LVT8986PM ,3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) Tap TransceiverFEATURES• Members of the Texas Instruments (TI) Family • Bypass (BYP –BYP ) Forces Primary to5 0of ..
74AVC8T245DGVRE4-74AVC8T245RHLRG4-SN74AVC8T245DGVR-SN74AVC8T245PW-SN74AVC8T245PWR-SN74AVC8T245RHLR
8-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and 3-State Outputs 24-TVSOP -40 to 85
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SN74AVC8T245SCES517J –DECEMBER 2003–REVISED MARCH 2017
SN74AVC8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation
and 3-State Outputs Features Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Protection Exceeds JESD22 8000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) Control Inputs VIH/VIL Levels Are Referencedto
VCCA Voltage VCC Isolation Feature–If Either VCC InputIsat
GND, All I/O Ports Arein the High-Impedance
State Ioff Supports Partial Power-Down Mode Operation Fully Configurable Dual-Rail Design Allows Each
Portto Operate Over the Full 1.4-Vto 3.6-V
Power-Supply Range I/Os Are 4.6-V Tolerant Maximum Data Rates 170 Mbps (VCCA< 1.8Vor VCCB< 1.8V) 320 Mbps (VCCA≥ 1.8V and VCCB≥ 1.8V)
Applications Personal Electronic Industrial Enterprise Telecom
Logic Diagram (Positive Logic) DescriptionThis 8-bit noninverting bus transceiver uses two
separate configurable power-supply rails. The
SN74AVC8T245 is optimized to operate with
VCCA/VCCB set at 1.4V to 3.6 V. The deviceis
operational with VCCA/VCCB as low as 1.2V. TheA
portis designedto track VCCA. VCCA accepts any
supply voltage from 1.2Vto 3.6V. TheB portis
designed to track VCCB. VCCB accepts any supply
voltage from 1.2Vto 3.6V. This allows for universal
low-voltage bidirectional translation between anyof
the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage
nodes.
The SN74AVC8T245is designed for asynchronous
communication between data buses. The device
transmits data from theA busto theB busor from
theB busto theA bus, depending on the logic level the direction-control (DIR) input. The output-enable
(OE) input can be usedto disable the outputs so the
buses are effectively isolated.
The SN74AVC8T245is designed so that the control
pins (DIR and OE) are suppliedby VCCA.
The SN74AVC8T245 solutionis compatible witha
single-supply system and canbe replaced later witha
'245 function, with minimal printed circuit board
redesign.
This deviceis fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, thus preventing damaging current backflow
through the device whenitis powered down.
The VCC isolation feature ensures thatif either VCC
inputisat GND, both ports arein the high-impedance
state. ensure the high-impedance state during power up power down, OE shall be tiedto VCC througha
pullup resistor; the minimum valueof the resistoris
determined by the current-sinking capability of the
driver.
Device Information(1)
