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SN74AVC4T774PWR-SN74AVC4T774RGYR
4-Bit Dual-Supply Bus Transceiver With Configurable Voltage-Level Shifting and 3-State Outputs 16-VQFN -40 to 85
1.8V
0.1 µF0.1 µF
3.0V
SN74AVC4T774
SPI
Port SPI
PeripheralMOSI
MISO
CLK
VCCA VCCB
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SN74AVC4T774SCES693E –FEBRUARY 2008–REVISED OCTOBER 2017
SN74AVC4T774 4-Bit Dual-Supply Bus Transceiver With Configurable Voltage-Level
Shifting and 3-State Outputs With Independent Direction Control Inputs Features Each Channel Hasan Independent DIR Control
Input Control Inputs VIH/VIL Levels are Referencedto
VCCA Voltage Fully Configurable Dual-Rail Design Allows Each
Portto Operate Over the Full 1.2-Vto 3.6-V
Power-Supply Range I/Os are 4.6-V Tolerant Ioff Supports Partial Power-Down-Mode Operation Typical Data Rates 380 Mbps (1.8-Vto 3.3-V Translation) 200 Mbps (<1.8-Vto 3.3-V Translation) 200 Mbps (Translateto 2.5Vor 1.8V) 150 Mbps (Translateto 1.5V) 100 Mbps (Translateto 1.2V) Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Protection Exceeds the Following Levels
(Tested Per JESD 22) ±8000-V Human-Body Model (A114-A) 250-V Machine Model (A115-A) ±1500-V Charged-Device Model (C101)
Applications Personal Electronic Industrial Enterprise Telecom
DescriptionThis 4-bit noninverting bus transceiver uses two
separate configurable power-supply rails. TheA port designedto track VCCA. VCCA accepts any supply
voltage from 1.2Vto 3.6V. TheB portis designedto
track VCCB. VCCB accepts any supply voltage from 1.2 3.6V. The SN74AVC4T774is optimizedto operate
with VCCA/VCCB setat 1.4Vto 3.6V.Itis operational
with VCCA/VCCB as low as 1.2 V. This allows for
universal low-voltage bi-directional translation
between anyof the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and
3.3-V voltage nodes.
The SN74AVC4T774is designed for asynchronous
communication between data buses. The logic levels the direction-control (DIR) input and the output-
enable (OE) input activate either the B-port outputsor
the A-port outputsor place both output portsin the
high-impedance mode. The device transmits data
from theA busto theB bus when theB outputs are
activated, and from theB busto theA bus when the outputs are activated. The input circuitry on bothA
andB portsis always active and must havea logic
HIGHor LOW level appliedto prevent excess ICC and
ICCZ.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe datasheet.
Typical Application Schematic
