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SN74AUP1G80DBVR-SN74AUP1G80DBVT-SN74AUP1G80DCKR-SN74AUP1G80DCKRE4-SN74AUP1G80YZPR Fast Delivery,Good Price
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Partno Mfg Dc Qty AvailableDescript
SN74AUP1G80DBVRTIN/a225avaiLow-Power Single Postitive-Edge-Triggered D-Type Flip-Flop
SN74AUP1G80DBVTTI ?N/a22avaiLow-Power Single Postitive-Edge-Triggered D-Type Flip-Flop
SN74AUP1G80DCKRTIN/a43500avaiLow-Power Single Postitive-Edge-Triggered D-Type Flip-Flop
SN74AUP1G80DCKRTI Pb-freeN/a2690avaiLow-Power Single Postitive-Edge-Triggered D-Type Flip-Flop
SN74AUP1G80DCKRE4TIN/a780avaiLow-Power Single Postitive-Edge-Triggered D-Type Flip-Flop 5-SC70 -40 to 85
SN74AUP1G80YZPRTIN/a504avaiLow-Power Single Postitive-Edge-Triggered D-Type Flip-Flop 5-DSBGA -40 to 85


SN74AUP1G80DCKR ,Low-Power Single Postitive-Edge-Triggered D-Type Flip-FlopMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74AUP1G80DCKR ,Low-Power Single Postitive-Edge-Triggered D-Type Flip-FlopElectrical Characteristics: T = –40°C to +85°C....... 7A11.2 Layout Example....... 176.7 Timing Req ..
SN74AUP1G80DCKRE4 ,Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop 5-SC70 -40 to 85Logic Diagram (Positive Logic)CLKCLKQ QD D1An IMPORTANT NOTICE at the end of this data sheet addres ..
SN74AUP1G80YZPR ,Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop 5-DSBGA -40 to 85Maximum Ratings.. 49.1 Application Information........ 166.2 ESD Ratings........ 49.2 Typical Appli ..
SN74AUP1G97DCKR ,Low-Power Configurable Multiple-Function Gate/packaging.(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designate ..
SN74AUP1G97DCKRE4 ,Low-Power Configurable Multiple-Function Gate 6-SC70 -40 to 85FEATURES• Available in the Texas Instruments NanoStar™ • Wide Operating V Range of 0.8 V to 3.6 VCC ..
SN74LVT16646 ,3.3-V ABT 16-Bit Bus Transceivers and Registers With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74LVT16646DL ,3.3-V ABT 16-Bit Bus Transceivers and Registers With 3-State Outputs              SCBS149D ..
SN74LVT16835DL , 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74LVT16952 ,3.3-V ABT 16-Bit Registered Transceivers With 3-State OutputsNot Recommended For New Designs SN54LVT16952, SN74LVT16952 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS ..
SN74LVT16952DGGR ,3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LVT16952DGGR ,3.3-V ABT 16-Bit Registered Transceivers With 3-State OutputsNot Recommended For New Designs SN54LVT16952, SN74LVT16952 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS ..


SN74AUP1G80DBVR-SN74AUP1G80DBVT-SN74AUP1G80DCKR-SN74AUP1G80DCKRE4-SN74AUP1G80YZPR
Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop
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SN74AUP1G80

SCES593F –JULY 2004–REVISED JULY 2017
SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop Features
Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Performance Tested Per JESD22 2000-V Human-Body Model
(A114-B, ClassII) 1000-V Charged-Device Model (C101) Availablein the Texas Instruments NanoStar™
Package Low Static-Power Consumption
(ICC= 0.9 µA Maximum) Low Dynamic-Power Consumption
(Cpd= 4.3 pF Typicalat 3.3V) Low Input Capacitance (Ci= 1.5 pF Typical) Low Noise– Overshoot and Undershoot <10%of
VCC Ioff Supports Partial-Power-Down Mode Operation Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise Immunityat
the Input
(Vhys= 250 mV Typicalat 3.3V) Wide Operating VCC Rangeof 0.8Vto 3.6V Optimized for 3.3-V Operation 3.6-V I/O Tolerantto Support Mixed-Mode Signal
Operation tpd= 4.4ns Maximumat 3.3V Suitablefor Point-to-Point Applications Applications Home Automation Factory Automation Test and Measurement Enterprise Switching Telecom Infrastructure Description
The AUP family is TI's premier solution to the
industry's low-power needs in battery-powered
portable applications. This family assuresa low static-
and dynamic-power consumption across the entire
VCC rangeof 0.8Vto 3.6V, resultingin increased
battery life (see AUP– The Lowest-Power Family).
This product also maintains excellent signal integrity
(see Excellent Signal Integrity).
Thisisa single positive-edge-triggered D-type flip-
flop. When dataat the data (D) input meets the setup
time requirement, the datais transferredto theQ
output on the positive-going edgeof the clock pulse.
Clock triggering occursata voltage level andis not
directly relatedto the rise timeof the clock pulse.
Following the hold-time interval, dataat theD input
can be changed without affecting the levelsat the
outputs.
NanoStar™ package technology is a major
breakthroughinIC packaging concepts, using the die the package.
This deviceis fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs when the deviceis powered down. This
inhibits current backflow into the device which
prevents damageto the device.
Device Information(1)

(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Logic)
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