SN74AUP1G17DCKR ,Low-Power Single Schmitt-Trigger BufferFeatures 3 DescriptionThe AUP family of devices is TI's premier solution to1• Latch-Up Performance ..
SN74AUP1G17DCKRG4 ,Low-Power Single Schmitt-Trigger Buffer 5-SC70 -40 to 85 SCES579J–JUNE 2004–REVISED SEPTEMBER 20175 Pin Configuration and FunctionsDBV PackageDCK Package5- ..
SN74AUP1G17DCKT ,Low-Power Single Schmitt-Trigger BufferElectrical Characteristics....... 511.2 Layout Example....... 166.6 Switching Characteristics: C = ..
SN74AUP1G17DRLR , LOW - POWER SINGLE SCHMITT-TRIGGLER BUFFER
SN74AUP1G17YZPR ,Low-Power Single Schmitt-Trigger BufferMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74AUP1G240DBVR ,Low-Power Single Buffer/Driver with 3-State Output 5-SOT-23 -40 to 85Features 3 DescriptionThe AUP family is TI's premier solution to the1• Latch-Up Performance Exceeds ..
SN74LVT16245BDGGR ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsFEATURESSN54LVT16245B . . . WD PACKAGE• Member of the Texas Instruments Widebus™SN74LVT16245B . . . ..
SN74LVT16245BDGVR ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsSCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006(1)FUNCTION TABLE(each 8-bit section)CONTROL INPUTS OUT ..
SN74LVT16245BDL ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsLOGIC DIAGRAM (POSITIVE LOGIC)2412DIR1DIR48 251OE 2OE36471A1 2A12 131B1 2B1To Seven Other Channels ..
SN74LVT16245BGQLR ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsSN54LVT16245B,, SN74LVT16245B3.3-V ABT 16-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
SN74LVT16245BZRDR ,3.3-V ABT 16-Bit Bus Transceivers With 3-State Outputs 54-BGA MICROSTAR JUNIOR -40 to 85Maximum Ratingsover recommended operating free-air temperature range (unless otherwise noted)MIN MA ..
SN74LVT16500DGGR , 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74AUP1G17DCKR-SN74AUP1G17DCKRG4-SN74AUP1G17DCKT-SN74AUP1G17YZPR
Low-Power Single Schmitt-Trigger Buffer
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SN74AUP1G17SCES579J–JUNE 2004–REVISED SEPTEMBER 2017
SN74AUP1G17 Low-Power Single Schmitt-Trigger Buffer Features Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Performance Tested Per JESD22 2000-V Human-Body Model
(A114-B, ClassII) 1000-V Charged-Device Model (C101) Availablein the Texas Instruments NanoStar™
Package Low Static-Power Consumption
(ICC= 0.9 µA Maximum) Low Dynamic-Power Consumption
(Cpd= 4.4 pF Typicalat 3.3V) Low Input Capacitance (Ci= 1.5 pF Typical) Low Noise– Overshoot and Undershoot
<10%of VCC Ioff Supports Partial-Power-Down Mode Operation Includes Schmitt-Trigger Inputs Wide Operating VCC Rangeof 0.8Vto 3.6V Optimized for 3.3-V Operation 3.6-V I/O Tolerantto Support Mixed-Mode Signal
Operation tpd= 5.1ns Maximumat 3.3V Suitablefor Point-to-Point Applications
Applications Grid Infrastructure PC& Notebooks Tablets Factory Automation& Control Gaming Server
DescriptionThe AUP familyof devicesis TI's premier solutionto
the industry's low-power needsin battery-powered
portable applications. This family ensuresa very low
static- and dynamic-power consumption across the
entire VCC range of 0.8V to 3.6 V, resulting in
increased battery life. This product also maintains
excellent signal integrity (see AUP– The Lowest-
Power Family and Excellent Signal Integrity).
This device functions as an independent gate with
Schmitt-trigger inputs, which allows for slow input
transition and better switching-noise immunityat the
input.
NanoStar™ package technology is a major
breakthroughinIC packaging concepts, using the die the package.
This deviceis fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs when the deviceis powered down. This
inhibits current backflow into the device which
prevents damageto the device.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic) DRL, DRT, DRY, and YZP
Logic Diagram (Positive Logic)
(YFP Package)
