SN74AUP1G126DCKR ,Low-Power Single Bus Buffer Gate with 3-State Output 5-SC70 -40 to 85Electrical Characteristics....... 511.2 Layout Example....... 176.6 Switching Characteristics: C = ..
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SN74LVT16245B ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsSCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006DESCRIPTION/ORDERING INFORMATION (CONTINUED)The 'LVT162 ..
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SN74LVT16245BDGVR ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsSCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006(1)FUNCTION TABLE(each 8-bit section)CONTROL INPUTS OUT ..
SN74LVT16245BDL ,3.3-V ABT 16-Bit Bus Transceivers With 3-State OutputsLOGIC DIAGRAM (POSITIVE LOGIC)2412DIR1DIR48 251OE 2OE36471A1 2A12 131B1 2B1To Seven Other Channels ..
SN74AUP1G126DBVR-SN74AUP1G126DCKR
Low-Power Single Bus Buffer Gate with 3-State Output 5-SOT -40 to 85
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SN74AUP1G126SCES596G –JULY 2004–REVISED AUGUST 2017
SN74AUP1G126 Low-Power Single Bus Buffer Gate With Tri-State Output Features Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Performance Tested Per JESD 22− 2000-V Human-Body Model
(A114-B, ClassII) 1000-V Charged-Device Model (C101) Availablein the Texas Instruments NanoStar™
Package Low Static-Power Consumption
(ICC= 0.9 µA Maximum) Low Dynamic-Power Consumption
(Cpd=4 pF Typicalat 3.3V) Low Input Capacitance (Ci= 1.5 pF Typical) Low Noise– Overshoot and Undershoot
<10%of VCC Input-Disable Feature Allows Floating Input
Conditions Ioff Supports Partial-Power-Down Mode Operation Input Hysteresis Allows Slow Input Transition and
Better Switching Noise Immunityat Input Wide Operating VCC Rangeof 0.8Vto 3.6V Optimized for 3.3-V Operation 3.6-V I/O Tolerantto Support Mixed-Mode Signal
Operation tpd= 4.6ns Maximumat 3.3V Suitablefor Point-to-Point Applications
Applications Audio Dock: Portable BluRay™ Players and Home Theaters Personal Digital Assistant (PDA) Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital (SSD): Client and Enterprise High-Definition (HDTV) and Mice
DescriptionThe AUP family is TI's premier solution to the
industry's low-power needs in battery-powered
portable applications. This family assuresa very low
static and dynamic power consumption across the
entire VCC rangeof 0.8Vto 3.6V, resultingin an
increased battery life. This product also maintains
excellent signal integrity (see AUP– The Lowest-
Power Family and Excellent Signal Integrity).
This bus buffer gateisa single line driver witha3-
state output. The outputis disabled when the output-
enable (OE) inputis low. This device has the input-
disable feature, which allows floating input signals. assure the high-impedance state during power up power down, OE shouldbe tiedto GND througha
pulldown resistor; the minimum valueof the resistoris
determined by the current-sourcing capabilityof the
driver.
NanoStar™ package technology is a major
breakthroughinIC packaging concepts, using the die the package.
This deviceis fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs when the deviceis powered down. This
inhibits current backflow into the device which
prevents damageto the device.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
