SN74AUC1G125DCKR ,Single Bus Buffer Gate With 3-State OutputFeatures 3 DescriptionThis bus buffer gate is operational at 0.8-V to 2.7-V1• Latch-Up Performance ..
SN74AUC1G125YZPR ,Single Bus Buffer Gate With 3-State Output SCES382L–MARCH 2002–REVISED JUNE 20175 Pin Configuration and FunctionsDBV PackageDCK Package5-Pin ..
SN74AUC1G126DBVR ,Single Bus Buffer Gate With 3-State OutputFeatures 3 DescriptionThe SN74AUC1G126 bus buffer gate is operational1• Latch-Up Performance Exceed ..
SN74AUC1G126DCKR ,Single Bus Buffer Gate With 3-State OutputElectrical Characteristics....... 613.1 Documentation Support.... 176.6 Switching Characteristics: ..
SN74AUC1G126YEPR , SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AUC1G14DBVR ,Single Schmitt-Trigger InverterLogic Diagram (Positive Logic)2 4A Y1An IMPORTANT NOTICE at the end of this data sheet addresses av ..
SN74LVCHR16245A ,16-Bit Bus Transceiver With 3-State OutputsElectrical Characteristics....... 813.1 Trademarks..... 167.6 Switching Characteristics...... 913.2 ..
SN74LVCHR16245AGR ,16-Bit Bus Transceiver With 3-State OutputsMaximum Ratings . 612 Layout.... 157.2 Handling Ratings. 612.1 Layout Guidelines.... 157.3 Recommen ..
SN74LVCHR16245ALR ,16-Bit Bus Transceiver With 3-State Outputs SCAS582Q–NOVEMBER 1996–REVISED OCTOBER 20146 Pin Configuration and FunctionsDGG, DGV, OR DL PACKAG ..
SN74LVCHR16245ALR ,16-Bit Bus Transceiver With 3-State OutputsSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN74LVCHR16245ASCAS5 ..
SN74LVCR162245 ,16-Bit Bus Transceiver With 3-State OutputsMaximum Ratingsover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
SN74LVCR162245DGGR ,16-Bit Bus Transceiver With 3-State OutputsSCES047E–AUGUST 1995–REVISED MARCH 2005DESCRIPTION/ORDERING INFORMATION (CONTINUED)To ensure the hi ..
SN74AUC1G125DBVR-SN74AUC1G125DCKR-SN74AUC1G125YZPR
Single Bus Buffer Gate With 3-State Output 5-SOT-23 -40 to 85
Y1 4Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
SN74AUC1G125SCES382L –MARCH 2002–REVISED JUNE 2017
SN74AUC1G125 Single Bus Buffer Gate With 3-State Output Features Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) Availablein the Texas Instruments
NanoFree™ Package Optimized for 1.8-V Operation andIs 3.6-V I/O
Tolerantto Support Mixed-Mode Signal Operation Ioff Supports Partial Power Down Mode and Back
Drive Protection Sub-1-V Operable Maxtpdof 2.5nsat 1.8V Low Power Consumption, 10-µA Maximum ICC ±8-mA Output Driveat 1.8V
Applications Audio Dock: Portable Blu-Ray Player and Home Theater Embedded PC MP3 Player/Recorder (Portable Audio) Personal Digital Assistant (PDA) Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital Solid State Drive (SSD): Client and Enterprise TV: LCD/Digital and High-Definition (HDTV) Tablet: Enterprise Video Analytics: Server Wireless Headset, Keyboard, and Mouse
DescriptionThis bus buffer gateis operationalat 0.8-Vto 2.7-V
VCC, butis designed specifically for 1.65-Vto 1.95-V
VCC operation.
The SN74AUC1G125 deviceisa single line driver
witha 3-state output. The outputis disabled when the
output-enable (OE) inputis high. ensure the high-impedance state during power up power down, OE should be tiedto VCC througha
pullup resistor; the minimum valueof the resistoris
determined by the current-sinking capability of the
driver.
NanoFree™ package technology is a major
breakthroughinIC packaging concepts, using the die the package.
This deviceis fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device whenitis powered down.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
