SN74AUC16374DGGR ,16-Bit Edge-Triggered D-Type Flip-Flop With 3-State OutputsFEATURESDGG OR DGV PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family1CLK1 481OE• Op ..
SN74AUC1G00DBVR ,Single 2-Input Positive-NAND GateElectrical Characteristicsover recommended operating free-air temperature range (unless otherwise n ..
SN74AUC1G00DCKR ,Single 2-Input Positive-NAND Gate/sc/package.(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designat ..
SN74AUC1G00DCKR ,Single 2-Input Positive-NAND GateFEATURES• Available in the Texas Instruments • Low Power Consumption, 10-μA Max ICCNanoFree™ Packag ..
SN74AUC1G00DRLR ,Single 2-Input Positive-NAND Gate 5-SOT -40 to 85SCES368O–SEPTEMBER 2001–REVISED JANUARY 2007(1)Recommended Operating ConditionsMIN MAX UNITV Supply ..
SN74AUC1G02DBVR ,Single 2-Input Positive-NOR GateFEATURES• Available in the Texas Instruments • Low Power Consumption, 10-μA Max ICCNanoFree™ Packag ..
SN74LVCH244APWR ,Octal Buffer/Driver With 3-State OutputsFEATURES• Operate From 1.65 V to 3.6 V • I Supports Partial-Power-Down ModeoffOperation• Inputs Acc ..
SN74LVCH244ARGYR ,Octal Buffer/Driver With 3-State OutputsSCES009O–JULY 1995–REVISED FEBRUARY 2007ORDERING INFORMATION(1)T PACKAGE ORDERABLE PART NUMBER TOP- ..
SN74LVCH244ARGYR ,Octal Buffer/Driver With 3-State OutputsSCES009O–JULY 1995–REVISED FEBRUARY 2007
SN74LVCH245A ,Octal Bus Transceiver With 3-State Outputs SCES008P–JULY 1995–REVISED JULY 20146 Pin Configuration and FunctionsSN54LVCH245A . . . J OR W PAC ..
SN74LVCH245ADBLE ,Octal Bus Transceiver With 3-State OutputsFeatures 2 Applications1• Operate From 1.65 V to 3.6 V • Servers• Inputs Accept Voltages to 5.5 V • ..
SN74LVCH245ADBR ,Octal Bus Transceiver With 3-State OutputsElectrical Characteristics....... 713 Device and Documentation Support........ 147.6 Switching Char ..
SN74AUC16374DGGR
16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TSSOP -40 to 85
DESCRIPTION/ORDERING
DGG OR DGV PACKAGE
(TOP VIEW)1OE
1Q1
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1CLK
1D1
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK buffered (OE) input canbe usedto place the eight outputsin eithera normal logic state (highor
SN74AUC16374 EDGE-TRIGGERED D-TYPE FLIP-FLOP Member the Texas Instruments Widebus™
Family Optimized for 1.8-V Operation andIs 3.6-V I/O
Tolerant Support Mixed-Mode Signal Low Power Consumption, 20-μA Max ICC ±8-mA
Driveat 1.8V Latch-Up Exceeds 100 mA Per
JESD 78,II ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Model (A115-A) 1000-V Charged-Device Model (C101)
INFORMATIONThis 16-bit edge-triggered D-type flip-flop is
operational 0.8-Vto 2.7-VVCC, butis designed
specifically 1.65-Vto 1.95-VVCC operation.
The SN74AUC16374 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, working registers.It canbe usedas
two 8-bit or one 16-bit flip-flop. On the
positive transitionof the clock (CLK) input, theQ
outputsof flip-flop take on the logic levels setup the data inputs.
low logic levels)or the high-impedance state.In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and drive provide the capabilityto drive bus lines
without interfaceor pullup components. does not internal operationsof the latch. Old can be retainedor new data canbe entered while
the outputsin the high-impedance state.
ORDERING PACKAGE(1)(2) ORDERABLE PART NUMBER TOP-SIDE MARKINGTSSOP– DGG Reelof 2000 AUC16374 TVSOP– DGV Reelof 2000 MH374 Reelof 1000 MH374 packing quantities, thermal and PCB design guidelinesare availableat
www.ti.com/sc/package.the most current package ordering Option Addendumatthe endof this document,or seetheTI
