SN74AS194DR ,4-Bit Bidirectional Universal Shift Registers SDAS212A − DECEMBER 1983 − REVISED D ..
SN74AS20 ,Dual 4-Input Positive-NAND Gateslogic diagram (positive logic)11&1A 1A221B1B6641Y1Y 41C1C551D1D92A92A102B 81012 2Y 2B82C 2Y122C132D ..
SN74AS20D ,Dual 4-Input Positive-NAND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74AS20DR , DUAL 4-INPUT POSITIVE-NAND GATES
SN74AS20N ,Dual 4-Input Positive-NAND Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74AS20NSR ,Dual 4-Input Positive-NAND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LVC3G04DCUR ,Triple Inverter GateFEATURES DESCRIPTIONThis triple inverter is designed for 1.65-V to 5.5-V VCC2• Available in the Tex ..
SN74LVC3G04DCURG4 ,Triple Inverter Gate 8-VSSOP -40 to 125maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74LVC3G04YZPR ,Triple Inverter GateMaximum Ratingsover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
SN74LVC3G06DCTR ,Triple Inverter Buffer/Driver with Open-Drain OutputMaximum Ratingsover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
SN74LVC3G06DCUR ,Triple Inverter Buffer/Driver with Open-Drain Outputmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74LVC3G06DCURG4 ,Triple Inverter Buffer/Driver with Open-Drain Output 8-VSSOP -40 to 125Electrical Characteristicsover recommended operating free-air temperature range (unless otherwise n ..
SN74AS194DR
4-Bit Bidirectional Universal Shift Registers
Direct Overriding Clear Temporary Data-Latching Capability Package Options Include PlasticSmall-Outline Packages (D), Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
descriptionThese 4-bit bidirectional universal shift registers
feature parallel outputs, right-shift and left-shift
serial (SR SER, SL SER) inputs, operating-
mode-control (S0, S1) inputs, and a direct
overriding clear (CLR) line. The registers have
four distinct modes of operation: Inhibit clock (temporary data latch/do nothing) Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Parallel (broadside) load
Parallel synchronous loading is accomplished by
applying the four bits of data and taking both S0
and S1 high. The data is loaded into the
associated flip-flops and appears at the outputs
after the positive transition of the clock (CLK)
input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left
synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when
both mode-control inputs are low.
The SN54AS194 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74AS194 is characterized for operation from 0°C to 70°C.
SL SER
GNDA
CLKB
CLK
SR SERCLRNCS1
SER
GND
NC − No internal connection
SN54AS194 ...FK PACKAGE
(TOP VIEW)
