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SN74ALVTH16374GRTEXASN/a11avai2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs


SN74ALVTH16374GR ,2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State OutputsFEATURESSN54ALVTH16374...WD PACKAGESN74ALVTH16374...DGG, DGV, OR DL PACKAGE• State-of-the-Art Advan ..
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SN74LVC2G157DCUT ,Single 2-Line to 1-Line Data Selector/MultiplexerFeatures... 18.3 Feature Description...... 82 Applications..... 18.4 Device Functional Modes...... ..
SN74LVC2G157YEAR , SINGL 2LINE TO 1LINE DATA SELECTOR/MULTIPLEXER


SN74ALVTH16374GR
2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs
FEATURES SN54ALVTH16374...WD PACKAGE
PACKAGE
(TOP VIEW)
SN74ALVTH16374...DGG, DGV, OR DL

1OE 1CLK
1Q1 1D1
1Q2 1D2
GND GND
1Q3 1D3
1Q4 1D4
VCC VCC
1Q5 1D5
1Q6 1D6
GND GND
1Q7 1D7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK1234567891011
DESCRIPTION/ORDERING INFORMATION
SN54ALVTH16374,, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus™ Design for 2.5-V
and 3.3-V Operation and Low Static Power
Dissipation
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With 2.3-Vto
3.6-VVCC)
Typical VOLP (Output Ground Bounce) <0.8V VCC= 3.3V,TA= 25°C High Drive (–24/24 mAat 2.5-VVCC and –32/64at 3.3-V) Power Off Disables Outputs, Permitting Live
Insertion
High-Impedance State During Power Up and
Power Down Prevents Driver Conflict
Uses Bus Hold on Data Inputsin Placeof
External Pullup/Pulldown Resistorsto Prevent
the Bus From Floating
Auto3-State Eliminates Bus Current Loading
When Output Exceeds VCC+ 0.5V
Latch-Up Performance Exceeds 250 mA Per
JESD17
ESD Protection Exceeds 2000V Per MIL-STD-883, Method
3015 Exceeds 200V Using Machine Model Exceeds 1000V Using Charged-Device
Model, Robotic Method
Flow-Through Architecture Facilitates Printed
Circuit Board Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink Small-Outline
(DGG), Thin Very Small-Outline (DGV)
Packages, and 380-mil Fine-Pitch Ceramic Flat
(WD) Package
devices are 16-bit edge-triggered flip-flops with 3-state outputs designed for 2.5-Vor VCC operation, but with the capabilityto providea TTL interfacetoa 5-V system environment. These are particularly for implementing registers, I/O ports, bidirectional drivers, and registers. devices can two flip-flop. On the positive transitionof the clock
(CLK), the flip-flops data (D) inputs.
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