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SN74ALVCH16835TIN/a50avai18-Bit Universal Bus Driver With 3-State Outputs
SN74ALVCH16835DGGRTIN/a28000avai18-Bit Universal Bus Driver With 3-State Outputs
SN74ALVCH16835DGGRTEXASN/a1980avai18-Bit Universal Bus Driver With 3-State Outputs


SN74ALVCH16835DGGR ,18-Bit Universal Bus Driver With 3-State OutputsMAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
SN74ALVCH16835DGGR ,18-Bit Universal Bus Driver With 3-State OutputsFEATURESDGG, DGV, OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family1 56NC GND ..
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SN74ALVCH16835-SN74ALVCH16835DGGR
18-Bit Universal Bus Driver With 3-State Outputs
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES053J–SEPTEMBER 1995–REVISED OCTOBER 2004 FEATURES DGG, DGV, OR DL PACKAGE • Member of the Texas Instruments Widebus™ (TOP VIEW) Family 1 56 NC GND • Operates From 1.65 V to 3.6 V NC 2 55 NC • Max t of 3.6 ns at 3.3 V pd Y1 3 54 A1 • ±24-mA Output Drive at 3.3 V 4 53 GND GND • Bus Hold on Data Inputs Eliminates the Need 5 52 Y2 A2 for External Pullup/Pulldown Resistors 6 51 Y3 A3 • Latch-Up Performance Exceeds 250 mA Per 7 50 V V CC CC JESD 17 Y4 8 49 A4 • ESD Protection Exceeds JESD 22 Y5 9 48 A5 - 2000-V Human-Body Model (A114-A) Y6 10 47 A6 - 200-V Machine Model (A115-A) 11 46 GND GND 12 45 Y7 A7 DESCRIPTION/ORDERING INFORMATION 13 44 Y8 A8 14 43 Y9 A9 This 18-bit universal bus driver is designed for 1.65-V Y10 15 42 A10 to 3.6-V V operation. CC Y11 16 41 A11 Data flow from A to Y is controlled by the 17 40 Y12 A12 output-enable (OE) input. The device operates in the 18 39 GND GND transparent mode when the latch-enable (LE) input is 19 38 Y13 A13 high. The A data is latched if the clock (CLK) input is 20 37 Y14 A14 held at a high or low logic level. If LE is low, the A Y15 21 36 A15 data is stored in the latch/flip-flop on the low-to-high V 22 35 V transition of CLK. When OE is high, the outputs are in CC CC the high-impedance state. Y16 23 34 A16 24 33 Y17 A17 To ensure the high-impedance state during power up 25 32 GND GND or power down, OE should be tied to V through a CC 26 31 Y18 A18 pullup resistor; the minimum value of the resistor is 27 30 OE CLK determined by the current-sinking capability of the driver. LE 28 29 GND Active bus-hold circuitry holds unused or undriven NC − No internal connection inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not xxxx recommended. xxxx ORDERING INFORMATION (1) T PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING A Tube SN74ALVCH16835DL SSOP - DL ALVCH16835 Tape and reel SN74ALVCH16835DLR TSSOP - DGG Tape and reel SN74ALVCH16835DGGR ALVCH16835 -40°C to 85°C TVSOP - DGV Tape and reel SN74ALVCH16835DGVR VH835 VFBGA - GQL SN74ALVCH16835KR Tape and reel VH835 VFBGA - ZQL (Pb-free) 74ALVCH16835ZQLR (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1995–2004, Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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